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llvm-mirror/test/Transforms/LoopVectorize/AArch64
2017-02-07 19:34:24 +00:00
..
aarch64-predication.ll [LV] Scalarize operands of predicated instructions 2016-12-07 15:03:32 +00:00
aarch64-unroll.ll
arbitrary-induction-step.ll [LV] Unify vector and scalar maps 2016-08-24 18:23:17 +00:00
arm64-unroll.ll
backedge-overflow.ll Re-commit [SCEV] Introduce a guarded backedge taken count and use it in LAA and LV 2016-04-08 14:29:09 +00:00
deterministic-type-shrinkage.ll
first-order-recurrence.ll [LV] Move insertelement sequence after scalar definitions 2016-08-29 20:14:04 +00:00
gather-cost.ll Second attempt at r285517. 2016-10-31 13:17:31 +00:00
interleaved_cost.ll [LV] Add new ARM/AArch64 interleaved access cost model tests (NFC) 2017-02-07 19:34:24 +00:00
lit.local.cfg
loop-vectorization-factors.ll Revert "[VectorUtils] Query number of sign bits to allow more truncations" 2016-05-10 12:27:23 +00:00
max-vf-for-interleaved.ll [LAA] Rename forwarding conflict detection option (NFC) 2016-05-16 17:00:56 +00:00
predication_costs.ll Reapply "[LV] Enable vectorization of loops with conditional stores by default" 2016-12-16 19:12:02 +00:00
reduction-small-size.ll
sdiv-pow2.ll
type-shrinkage-insertelt.ll