mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 05:01:59 +01:00
90ca961862
Errors like the following are reported by: https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_llvm-2Dclang-2Dx86-5F64-2Dexpensive-2Dchecks-2Dwin_builds_11261&d=DwIBAg&c=5VD0RTtNlTh3ycd41b3MUw&r=DA8e1B5r073vIqRrFz7MRA&m=929oWPCf7Bf2qQnir4GBtowB8ZAlIRWsAdTfRkDaK-g&s=9k-wbEUVpUm474hhzsmAO29VXVvbxJPWD9RTgCD71fQ&e= *** Bad machine code: Explicit definition marked as use *** - function: cal_align1 - basic block: %bb.0 entry (0x47edd98) - instruction: LDB $r3, $r2, 0 - operand 0: $r3 This is because RegState info was missing for ScratchReg inside expandMEMCPY. This caused incomplete register usage information to MachineInstr verifier which then would complain as there could be potential code-gen issue if the complained MachineInstr is used in place where register usage information matters even though the memcpy expanding is not in such case as it happens at the last stage of IR optimization pipeline. We should always specify those register usage information which compiler couldn't deduct automatically whenever we add a hardware register manually. Reported-by: Builder llvm-clang-x86_64-expensive-checks-win Build #11261 Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 338134
117 lines
4.6 KiB
LLVM
117 lines
4.6 KiB
LLVM
; RUN: llc < %s -march=bpfel -verify-machineinstrs -bpf-expand-memcpy-in-order | FileCheck %s
|
|
; RUN: llc < %s -march=bpfeb -verify-machineinstrs -bpf-expand-memcpy-in-order | FileCheck %s
|
|
;
|
|
; #define COPY_LEN 9
|
|
;
|
|
; void cal_align1(void *a, void *b)
|
|
; {
|
|
; __builtin_memcpy(a, b, COPY_LEN);
|
|
; }
|
|
;
|
|
; void cal_align2(short *a, short *b)
|
|
; {
|
|
; __builtin_memcpy(a, b, COPY_LEN);
|
|
; }
|
|
;
|
|
; #undef COPY_LEN
|
|
; #define COPY_LEN 19
|
|
; void cal_align4(int *a, int *b)
|
|
; {
|
|
; __builtin_memcpy(a, b, COPY_LEN);
|
|
; }
|
|
;
|
|
; #undef COPY_LEN
|
|
; #define COPY_LEN 27
|
|
; void cal_align8(long long *a, long long *b)
|
|
; {
|
|
; __builtin_memcpy(a, b, COPY_LEN);
|
|
; }
|
|
|
|
; Function Attrs: nounwind
|
|
define dso_local void @cal_align1(i8* nocapture %a, i8* nocapture readonly %b) local_unnamed_addr #0 {
|
|
entry:
|
|
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 9, i1 false)
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: argmemonly nounwind
|
|
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1
|
|
|
|
; CHECK: [[SCRATCH_REG:r[0-9]]] = *(u8 *)([[SRC_REG:r[0-9]]] + 0)
|
|
; CHECK: *(u8 *)([[DST_REG:r[0-9]]] + 0) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 1)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 1) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 2)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 2) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 3)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 3) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 4)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 4) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 5)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 5) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 6)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 6) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 7)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 7) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 8)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 8) = [[SCRATCH_REG]]
|
|
|
|
; Function Attrs: nounwind
|
|
define dso_local void @cal_align2(i16* nocapture %a, i16* nocapture readonly %b) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = bitcast i16* %a to i8*
|
|
%1 = bitcast i16* %b to i8*
|
|
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 %0, i8* align 2 %1, i64 9, i1 false)
|
|
ret void
|
|
}
|
|
; CHECK: [[SCRATCH_REG:r[0-9]]] = *(u16 *)([[SRC_REG:r[0-9]]] + 0)
|
|
; CHECK: *(u16 *)([[DST_REG:r[0-9]]] + 0) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u16 *)([[SRC_REG]] + 2)
|
|
; CHECK: *(u16 *)([[DST_REG]] + 2) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u16 *)([[SRC_REG]] + 4)
|
|
; CHECK: *(u16 *)([[DST_REG]] + 4) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u16 *)([[SRC_REG]] + 6)
|
|
; CHECK: *(u16 *)([[DST_REG]] + 6) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 8)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 8) = [[SCRATCH_REG]]
|
|
|
|
; Function Attrs: nounwind
|
|
define dso_local void @cal_align4(i32* nocapture %a, i32* nocapture readonly %b) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = bitcast i32* %a to i8*
|
|
%1 = bitcast i32* %b to i8*
|
|
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 19, i1 false)
|
|
ret void
|
|
}
|
|
; CHECK: [[SCRATCH_REG:r[0-9]]] = *(u32 *)([[SRC_REG:r[0-9]]] + 0)
|
|
; CHECK: *(u32 *)([[DST_REG:r[0-9]]] + 0) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u32 *)([[SRC_REG]] + 4)
|
|
; CHECK: *(u32 *)([[DST_REG]] + 4) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u32 *)([[SRC_REG]] + 8)
|
|
; CHECK: *(u32 *)([[DST_REG]] + 8) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u32 *)([[SRC_REG]] + 12)
|
|
; CHECK: *(u32 *)([[DST_REG]] + 12) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u16 *)([[SRC_REG]] + 16)
|
|
; CHECK: *(u16 *)([[DST_REG]] + 16) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 18)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 18) = [[SCRATCH_REG]]
|
|
|
|
; Function Attrs: nounwind
|
|
define dso_local void @cal_align8(i64* nocapture %a, i64* nocapture readonly %b) local_unnamed_addr #0 {
|
|
entry:
|
|
%0 = bitcast i64* %a to i8*
|
|
%1 = bitcast i64* %b to i8*
|
|
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %0, i8* align 8 %1, i64 27, i1 false)
|
|
ret void
|
|
}
|
|
; CHECK: [[SCRATCH_REG:r[0-9]]] = *(u64 *)([[SRC_REG:r[0-9]]] + 0)
|
|
; CHECK: *(u64 *)([[DST_REG:r[0-9]]] + 0) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u64 *)([[SRC_REG]] + 8)
|
|
; CHECK: *(u64 *)([[DST_REG]] + 8) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u64 *)([[SRC_REG]] + 16)
|
|
; CHECK: *(u64 *)([[DST_REG]] + 16) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u16 *)([[SRC_REG]] + 24)
|
|
; CHECK: *(u16 *)([[DST_REG]] + 24) = [[SCRATCH_REG]]
|
|
; CHECK: [[SCRATCH_REG]] = *(u8 *)([[SRC_REG]] + 26)
|
|
; CHECK: *(u8 *)([[DST_REG]] + 26) = [[SCRATCH_REG]]
|