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7a3a160940
Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
123 lines
2.7 KiB
LLVM
123 lines
2.7 KiB
LLVM
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as | FileCheck %s
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; Radar 7449043
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%struct.int32x4_t = type { <4 x i32> }
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define void @t() nounwind {
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entry:
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; CHECK: vmov.I64 q15, #0
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; CHECK: vmov.32 d30[0],
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; CHECK: vmov q8, q15
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%tmp = alloca %struct.int32x4_t, align 16
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call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
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ret void
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}
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; Radar 7457110
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%struct.int32x2_t = type { <4 x i32> }
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define void @t2() nounwind {
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entry:
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; CHECK: vmov d30, d16
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; CHECK: vmov.32 r0, d30[0]
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%asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
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ret void
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}
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; Radar 9306086
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%0 = type { <8 x i8>, <16 x i8>* }
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define hidden void @conv4_8_E() nounwind {
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entry:
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%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
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unreachable
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}
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; Radar 9037836 & 9119939
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define i32 @t3() nounwind {
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entry:
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tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind
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ret i32 0
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}
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; Radar 9037836 & 9119939
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@k.2126 = internal unnamed_addr global float 1.000000e+00
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define i32 @t4() nounwind {
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entry:
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call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind
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ret i32 0
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}
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; Radar 9037836 & 9119939
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define i32 @t5() nounwind {
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entry:
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call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
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ret i32 0
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}
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; Radar 9307836 & 9119939
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define float @t6(float %y) nounwind {
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entry:
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; CHECK: t6
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; CHECK: flds s15, s0
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%0 = tail call float asm "flds s15, $0", "=x"() nounwind
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ret float %0
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}
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; Radar 9307836 & 9119939
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define double @t7(double %y) nounwind {
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entry:
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; CHECK: t7
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; CHECK: flds s15, d0
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%0 = tail call double asm "flds s15, $0", "=x"() nounwind
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ret double %0
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}
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; Radar 9307836 & 9119939
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define float @t8(float %y) nounwind {
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entry:
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; CHECK: t8
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; CHECK: flds s15, s0
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%0 = tail call float asm "flds s15, $0", "=t"() nounwind
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ret float %0
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}
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; Radar 9307836 & 9119939
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define i32 @t9(i32 %r0) nounwind {
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entry:
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; CHECK: t9
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; CHECK: movw r0, #27182
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%0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
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ret i32 %0
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}
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; Radar 9866494
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define void @t10(i8* %f, i32 %g) nounwind {
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entry:
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; CHECK: t10
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; CHECK: str r1, [r0]
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%f.addr = alloca i8*, align 4
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store i8* %f, i8** %f.addr, align 4
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call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
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ret void
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}
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; Radar 10551006
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define <4 x i32> @t11(i32* %p) nounwind {
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entry:
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; CHECK: t11
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; CHECK: vld1.s32 {d16[], d17[]}, [r0]
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%0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
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ret <4 x i32> %0
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}
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