mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
4c043c50fd
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
llvm-svn: 100384
67 lines
2.0 KiB
C++
67 lines
2.0 KiB
C++
//===- InstrInfoEmitter.h - Generate a Instruction Set Desc. ----*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This tablegen backend is responsible for emitting a description of the target
|
|
// instruction set for the code generator.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef INSTRINFO_EMITTER_H
|
|
#define INSTRINFO_EMITTER_H
|
|
|
|
#include "TableGenBackend.h"
|
|
#include "CodeGenDAGPatterns.h"
|
|
#include <vector>
|
|
#include <map>
|
|
|
|
namespace llvm {
|
|
|
|
class StringInit;
|
|
class IntInit;
|
|
class ListInit;
|
|
class CodeGenInstruction;
|
|
|
|
class InstrInfoEmitter : public TableGenBackend {
|
|
RecordKeeper &Records;
|
|
CodeGenDAGPatterns CDP;
|
|
std::map<std::string, unsigned> ItinClassMap;
|
|
|
|
public:
|
|
InstrInfoEmitter(RecordKeeper &R) : Records(R), CDP(R) { }
|
|
|
|
// run - Output the instruction set description, returning true on failure.
|
|
void run(raw_ostream &OS);
|
|
|
|
private:
|
|
typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy;
|
|
|
|
void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
|
|
Record *InstrInfo,
|
|
std::map<std::vector<Record*>, unsigned> &EL,
|
|
std::map<Record*, unsigned> &BM,
|
|
const OperandInfoMapTy &OpInfo,
|
|
raw_ostream &OS);
|
|
|
|
// Itinerary information.
|
|
void GatherItinClasses();
|
|
unsigned getItinClassNumber(const Record *InstRec);
|
|
|
|
// Operand information.
|
|
void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs);
|
|
std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
|
|
|
|
void DetectRegisterClassBarriers(std::vector<Record*> &Defs,
|
|
const std::vector<CodeGenRegisterClass> &RCs,
|
|
std::vector<Record*> &Barriers);
|
|
};
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|