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llvm-mirror/test/CodeGen/MSP430/misched-msp430.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

21 lines
575 B
LLVM

; RUN: llc < %s -mtriple=msp430-unknown-unknown -enable-misched | FileCheck %s
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
@y = common global i16 0, align 2
@x = common global i16 0, align 2
; Test that the MI Scheduler's initPolicy does not crash when i32 is
; unsupported. The content of the asm check below is unimportant. It
; only verifies that the code generator ran successfully.
;
; CHECK-LABEL: @f
; CHECK: mov.w &y, &x
; CHECK: ret
define void @f() {
entry:
%0 = load i16, i16* @y, align 2
store i16 %0, i16* @x, align 2
ret void
}