mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
314fb415b4
ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
29 lines
914 B
LLVM
29 lines
914 B
LLVM
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
|
|
; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
|
|
; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
|
|
; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB
|
|
; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
|
|
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
|
|
|
|
define i32 @test_return(i32 %a) nounwind readnone {
|
|
entry:
|
|
; ARM-LABEL: test_return
|
|
; ARM: mov pc
|
|
; THUMB-LABEL: test_return
|
|
; THUMB: bx
|
|
ret i32 %a
|
|
}
|
|
|
|
@helper = global i32 ()* null, align 4
|
|
|
|
define i32 @test_indirect() #0 {
|
|
entry:
|
|
; ARM-LABEL: test_indirect
|
|
; ARM: mov pc
|
|
; THUMB-LABEL: test_indirect
|
|
; THUMB: bx
|
|
%0 = load i32 ()*, i32 ()** @helper, align 4
|
|
%call = tail call i32 %0()
|
|
ret i32 %call
|
|
}
|