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llvm-mirror/test/CodeGen/ARM/pr36577.ll
Sanjay Patel f60a29f8fa [DAGCombiner] form 'not' ops ahead of shifts (PR39657)
We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'),
but that would not matter without this patch because DAGCombiner was 
reversing that transform. I think we need this transform in the backend 
regardless of what happens in IR to catch cases where the shift-xor 
is formed late from GEP or other ops.

https://rise4fun.com/Alive/NC1

  Name: shl
  Pre: (-1 << C2) == C1
  %shl = shl i8 %x, C2
  %r = xor i8 %shl, C1
  =>
  %not = xor i8 %x, -1
  %r = shl i8 %not, C2
  
  Name: shr
  Pre: (-1 u>> C2) == C1
  %sh = lshr i8 %x, C2
  %r = xor i8 %sh, C1
  =>
  %not = xor i8 %x, -1
  %r = lshr i8 %not, C2

https://bugs.llvm.org/show_bug.cgi?id=39657

llvm-svn: 347478
2018-11-22 19:24:10 +00:00

28 lines
941 B
LLVM

; RUN: llc -mtriple armv6t2 %s -o - | FileCheck %s
; RUN: llc -mtriple thumbv6t2 %s -o - | FileCheck %s --check-prefix=CHECK-T2
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
; RUN: llc -mtriple thumbv7 %s -o - | FileCheck %s --check-prefix=CHECK-T2
; RUN: llc -mtriple thumbv7m %s -o - | FileCheck %s --check-prefix=CHECK-T2
; RUN: llc -mtriple thumbv8m.main %s -o - | FileCheck %s --check-prefix=CHECK-T2
@a = common dso_local local_unnamed_addr global i16 0, align 2
; CHECK-LABEL: pr36577
; CHECK: ldrh r0, [r0]
; CHECK: mvn r0, r0, lsr #7
; CHECK: orr r0, r1, r0, lsl #2
; CHECK-T2: ldrh r0, [r0]
; CHECK-T2: mvn.w r0, r0, lsr #7
; CHECK-T2: orr.w r0, r1, r0, lsl #2
define dso_local arm_aapcscc i32** @pr36577() {
entry:
%0 = load i16, i16* @a, align 2
%1 = lshr i16 %0, 7
%2 = and i16 %1, 1
%3 = zext i16 %2 to i32
%4 = xor i32 %3, -1
%add.ptr = getelementptr inbounds i32*, i32** null, i32 %4
ret i32** %add.ptr
}