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https://github.com/RPCS3/llvm-mirror.git
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cd4ff3e8fc
output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
73 lines
2.2 KiB
LLVM
73 lines
2.2 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
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; Test signed conversion.
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; CHECK-LABEL: @t0
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; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2
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; CHECK: bx lr
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define <2 x i32> @t0(<2 x float> %in) {
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%mul.i = fmul <2 x float> %in, <float 4.0, float 4.0>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test unsigned conversion.
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; CHECK-LABEL: @t1
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; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3
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; CHECK: bx lr
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define <2 x i32> @t1(<2 x float> %in) {
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%mul.i = fmul <2 x float> %in, <float 8.0, float 8.0>
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%vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test which should not fold due to non-power of 2.
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; CHECK-LABEL: @t2
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; CHECK: vmul
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; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bx lr
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define <2 x i32> @t2(<2 x float> %in) {
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entry:
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%mul.i = fmul <2 x float> %in, <float 0x401B333340000000, float 0x401B333340000000>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test which should not fold due to power of 2 out of range.
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; CHECK-LABEL: @t3
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; CHECK: vmul
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; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: bx lr
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define <2 x i32> @t3(<2 x float> %in) {
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%mul.i = fmul <2 x float> %in, <float 0x4200000000000000, float 0x4200000000000000>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test which case where const is max power of 2 (i.e., 2^32).
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; CHECK-LABEL: @t4
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; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #32
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; CHECK: bx lr
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define <2 x i32> @t4(<2 x float> %in) {
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%mul.i = fmul <2 x float> %in, <float 0x41F0000000000000, float 0x41F0000000000000>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test quadword.
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; CHECK-LABEL: @t5
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; CHECK: vcvt.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}, #3
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; CHECK: bx lr
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define <4 x i32> @t5(<4 x float> %in) {
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%mul.i = fmul <4 x float> %in, <float 8.0, float 8.0, float 8.0, float 8.0>
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%vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
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ret <4 x i32> %vcvt.i
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}
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; CHECK-LABEL: test_illegal_fp_to_int:
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; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2
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define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
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%scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
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%val = fptosi <3 x float> %scale to <3 x i32>
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ret <3 x i32> %val
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}
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