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2f3956c41c
When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
311 lines
8.2 KiB
LLVM
311 lines
8.2 KiB
LLVM
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; Function Attrs: norecurse nounwind
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define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%add = fadd fp128 %0, %0
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store fp128 %add, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpAdd
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; CHECK-NOT: bl __addtf3
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; CHECK: xsaddqp
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; CHECK: stxv
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpSub(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%sub = fsub fp128 %0, %0
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store fp128 %sub, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpSub
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; CHECK-NOT: bl __subtf3
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; CHECK: xssubqp
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; CHECK: stxv
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpMul(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%mul = fmul fp128 %0, %0
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store fp128 %mul, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpMul
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; CHECK-NOT: bl __multf3
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; CHECK: xsmulqp
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; CHECK: stxv
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpDiv(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%div = fdiv fp128 %0, %0
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store fp128 %div, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpDiv
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; CHECK-NOT: bl __divtf3
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; CHECK: xsdivqp
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; CHECK: stxv
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; CHECK: blr
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}
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define void @testLdNSt(i8* nocapture readonly %PtrC, fp128* nocapture %PtrF) {
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %PtrC, i64 4
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%0 = bitcast i8* %add.ptr to fp128*
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%1 = load fp128, fp128* %0, align 16
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%2 = bitcast fp128* %PtrF to i8*
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%add.ptr1 = getelementptr inbounds i8, i8* %2, i64 8
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%3 = bitcast i8* %add.ptr1 to fp128*
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store fp128 %1, fp128* %3, align 16
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ret void
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; CHECK-LABEL: testLdNSt
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; CHECK: lxvx
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; CHECK: stxvx
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; CHECK-NEXT blr
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}
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define void @qpSqrt(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.sqrt.f128(fp128 %0)
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store fp128 %1, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpSqrt
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; CHECK-NOT: bl sqrtl
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; CHECK: xssqrtqp
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; CHECK: stxv
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; CHECK: blr
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}
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declare fp128 @llvm.sqrt.f128(fp128 %Val)
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define void @qpCpsgn(fp128* nocapture readonly %a, fp128* nocapture readonly %b,
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fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = tail call fp128 @llvm.copysign.f128(fp128 %0, fp128 %1)
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store fp128 %2, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpCpsgn
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; CHECK-NOT: rldimi
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; CHECK: xscpsgnqp
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; CHECK: stxv
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; CHECK: blr
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}
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declare fp128 @llvm.copysign.f128(fp128 %Mag, fp128 %Sgn)
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define void @qpAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
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store fp128 %1, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpAbs
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; CHECK-NOT: clrldi
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; CHECK: xsabsqp
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; CHECK: stxv
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; CHECK: blr
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}
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declare fp128 @llvm.fabs.f128(fp128 %Val)
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define void @qpNAbs(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.fabs.f128(fp128 %0)
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%neg = fsub fp128 0xL00000000000000008000000000000000, %1
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store fp128 %neg, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpNAbs
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; CHECK-NOT: bl __subtf3
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; CHECK: xsnabsqp
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; CHECK: stxv
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; CHECK: blr
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}
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define void @qpNeg(fp128* nocapture readonly %a, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%sub = fsub fp128 0xL00000000000000008000000000000000, %0
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store fp128 %sub, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpNeg
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; CHECK-NOT: bl __subtf3
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; CHECK: xsnegqp
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; CHECK: stxv
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; CHECK: blr
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}
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define fp128 @qp_sin(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_sin:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl sinf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.sin.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.sin.f128(fp128 %Val)
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define fp128 @qp_cos(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_cos:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl cosf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.cos.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.cos.f128(fp128 %Val)
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define fp128 @qp_log(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_log:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl logf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.log.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.log.f128(fp128 %Val)
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define fp128 @qp_log10(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_log10:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl log10f128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.log10.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.log10.f128(fp128 %Val)
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define fp128 @qp_log2(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_log2:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl log2f128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.log2.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.log2.f128(fp128 %Val)
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define fp128 @qp_minnum(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b) {
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; CHECK-LABEL: qp_minnum:
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; CHECK: lxv v2, 0(r3)
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; CHECK: lxv v3, 0(r4)
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; CHECK: bl fminf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = tail call fp128 @llvm.minnum.f128(fp128 %0, fp128 %1)
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ret fp128 %2
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}
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declare fp128 @llvm.minnum.f128(fp128 %Val0, fp128 %Val1)
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define fp128 @qp_maxnum(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b) {
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; CHECK-LABEL: qp_maxnum:
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; CHECK: lxv v2, 0(r3)
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; CHECK: lxv v3, 0(r4)
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; CHECK: bl fmaxf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = tail call fp128 @llvm.maxnum.f128(fp128 %0, fp128 %1)
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ret fp128 %2
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}
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declare fp128 @llvm.maxnum.f128(fp128 %Val0, fp128 %Val1)
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define fp128 @qp_pow(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b) {
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; CHECK-LABEL: qp_pow:
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; CHECK: lxv v2, 0(r3)
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; CHECK: lxv v3, 0(r4)
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; CHECK: bl powf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = tail call fp128 @llvm.pow.f128(fp128 %0, fp128 %1)
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ret fp128 %2
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}
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declare fp128 @llvm.pow.f128(fp128 %Val, fp128 %Power)
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define fp128 @qp_exp(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_exp:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl expf128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.exp.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.exp.f128(fp128 %Val)
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define fp128 @qp_exp2(fp128* nocapture readonly %a) {
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; CHECK-LABEL: qp_exp2:
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; CHECK: lxv v2, 0(r3)
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; CHECK: bl exp2f128
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = tail call fp128 @llvm.exp2.f128(fp128 %0)
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ret fp128 %1
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}
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declare fp128 @llvm.exp2.f128(fp128 %Val)
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define void @qp_powi(fp128* nocapture readonly %a, i32* nocapture readonly %b,
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fp128* nocapture %res) {
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; CHECK-LABEL: qp_powi:
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; CHECK: lxv v2, 0(r3)
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; CHECK: lwz r5, 0(r4)
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; CHECK: bl __powikf2
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; CHECK: blr
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load i32, i32* %b, align 8
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%2 = tail call fp128 @llvm.powi.f128(fp128 %0, i32 %1)
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store fp128 %2, fp128* %res, align 16
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ret void
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}
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declare fp128 @llvm.powi.f128(fp128 %Val, i32 %power)
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@a = common global fp128 0xL00000000000000000000000000000000, align 16
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@b = common global fp128 0xL00000000000000000000000000000000, align 16
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define fp128 @qp_frem() #0 {
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entry:
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%0 = load fp128, fp128* @a, align 16
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%1 = load fp128, fp128* @b, align 16
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%rem = frem fp128 %0, %1
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ret fp128 %rem
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; CHECK-LABEL: qp_frem
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; CHECK: bl fmodf128
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; CHECK: blr
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}
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