mirror of
https://github.com/RPCS3/llvm-mirror.git
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687a7c63f2
We use o suffix to indicate record form instuctions, (as it is similar to dot '.' in mne?) This was fine before, as we did not support XO-form. However, with https://reviews.llvm.org/D66902, we now have XO-form support. It becomes confusing now to still use 'o' for record form, and it is weird to have something like 'Oo' . This patch rename all 'o' instructions to use '_rec' instead. Also rename `isDot` to `isRecordForm`. Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail Differential Revision: https://reviews.llvm.org/D70758
417 lines
12 KiB
YAML
417 lines
12 KiB
YAML
# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
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# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - | FileCheck %s --check-prefix=CHECK-LATE
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--- |
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; ModuleID = 'rlwinm_rldicl_to_andi.ll'
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source_filename = "rlwinm_rldicl_to_andi.c"
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @testRLWINMSingleUseDef(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i32 %a, 1048575
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%tobool = icmp eq i32 %shl.mask, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @testRLWINMNoGPRUseZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i32 %a, 1048575
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%tobool = icmp eq i32 %shl.mask, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @testRLWINMNoGPRUseNonZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i32 %a, 1048575
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%tobool = icmp eq i32 %shl.mask, 0
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%cond = select i1 %tobool, i32 %a, i32 %b
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ret i32 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLSingleUseDef(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i64 %a, 4503599627370495
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%tobool = icmp eq i64 %shl.mask, 0
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%cond = select i1 %tobool, i64 %a, i64 %b
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ret i64 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLNoGPRUseZero(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i64 %a, 4503599627370495
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%tobool = icmp eq i64 %shl.mask, 0
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%cond = select i1 %tobool, i64 %a, i64 %b
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ret i64 %cond
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @testRLDICLNoGPRUseNonZero(i64 %a, i64 %b) local_unnamed_addr #0 {
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entry:
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%shl.mask = and i64 %a, 4503599627370495
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%tobool = icmp eq i64 %shl.mask, 0
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%cond = select i1 %tobool, i64 %a, i64 %b
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ret i64 %cond
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}
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attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"PIC Level", i32 2}
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!2 = !{!"clang version 7.0.0 (trunk 322378)"}
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...
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---
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name: testRLWINMSingleUseDef
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# CHECK: testRLWINMSingleUseDef
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# CHECK-LATE: testRLWINMSingleUseDef
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc, preferred-register: '' }
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- { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc = COPY $x4
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%0:g8rc = COPY $x3
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%2:gprc_and_gprc_nor0 = COPY %1.sub_32
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%3:gprc = LI -11
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%4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
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; CHECK: LI 4055
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; CHECK: ANDI_rec %3, 4055
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rlwinm.
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%5:crrc = COPY killed $cr0
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%6:gprc = ISEL %4, %2, %5.sub_eq
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%7:g8rc = EXTSW_32_64 killed %6
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLWINMNoGPRUseZero
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 4, class: gprc, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc = COPY $x4
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%0:g8rc = COPY $x3
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%2:gprc_and_gprc_nor0 = COPY %1.sub_32
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%3:gprc_and_gprc_nor0 = LI 1
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%4:gprc = RLWINM_rec %3, 21, 20, 31, implicit-def $cr0
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; CHECK: LI 1
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; CHECK: ANDI_rec %3, 0
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; CHECK-LATE: li [[IMM:[0-9]+]], 1
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; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
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%5:crrc = COPY killed $cr0
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%6:gprc = ISEL %3, %2, %5.sub_eq
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%7:g8rc = EXTSW_32_64 killed %6
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLWINMNoGPRUseNonZero
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc, preferred-register: '' }
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- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 4, class: gprc, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: gprc, preferred-register: '' }
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- { id: 7, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc = COPY $x4
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%0:g8rc = COPY $x3
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%2:gprc_and_gprc_nor0 = COPY %1.sub_32
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%3:gprc_and_gprc_nor0 = LI -11
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%4:gprc = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
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; CHECK: LI -11
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; CHECK: ANDI_rec %3, 65525
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rlwinm.
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%5:crrc = COPY killed $cr0
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%6:gprc = ISEL %3, %2, %5.sub_eq
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%7:g8rc = EXTSW_32_64 killed %6
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$x3 = COPY %7
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLDICLSingleUseDef
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 3, class: crrc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc_and_g8rc_nox0 = COPY $x4
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%0:g8rc = LI8 -11
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%2:g8rc_and_g8rc_nox0 = RLDICL_rec %0, 2, 49, implicit-def $cr0
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; CHECK: LI8 32727
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; CHECK: ANDI8_rec %0, 32727
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rldicl.
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%3:crrc = COPY killed $cr0
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%4:g8rc = ISEL8 %2, %1, %3.sub_eq
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$x3 = COPY %4
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLDICLNoGPRUseZero
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: crrc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc_and_g8rc_nox0 = COPY $x4
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%0:g8rc_and_g8rc_nox0 = LI8 1
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%2:g8rc = RLDICL_rec %0, 32, 33, implicit-def $cr0
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; CHECK: LI8 1
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; CHECK: ANDI8_rec %0, 0
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; CHECK-LATE: li [[IMM:[0-9]+]], 1
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; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
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%3:crrc = COPY killed $cr0
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%4:g8rc = ISEL8 %0, %1, %3.sub_eq
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$x3 = COPY %4
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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---
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name: testRLDICLNoGPRUseNonZero
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: crrc, preferred-register: '' }
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- { id: 4, class: g8rc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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- { reg: '$x4', virtual-reg: '%1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: $x3, $x4
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%1:g8rc_and_g8rc_nox0 = COPY $x4
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%0:g8rc_and_g8rc_nox0 = LI8 -11
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%2:g8rc = RLDICL_rec %0, 2, 49, implicit-def $cr0
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; CHECK: LI8 -11
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; CHECK: ANDI8_rec %0, 65525
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; CHECK-LATE-NOT: andi.
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; CHECK-LATE: rldicl.
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%3:crrc = COPY killed $cr0
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%4:g8rc = ISEL8 %0, %1, %3.sub_eq
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$x3 = COPY %4
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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