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22d9d7e438
This patch exploits the instructions that store a single element from a vector to preform a (store (extract_elt)). We already have code that does this with ISA 3.0 instructions that were added to handle i8/i16 types. However, we had never exploited the existing ones that handle f32/f64/i32/i64 types. Differential revision: https://reviews.llvm.org/D56175 llvm-svn: 352131
124 lines
3.9 KiB
LLVM
124 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE
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; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE
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define void @test_liwzx1(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
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; P9LE-LABEL: test_liwzx1:
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; P9LE: # %bb.0:
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; P9LE-NEXT: lfiwzx f0, 0, r3
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; P9LE-NEXT: lfiwzx f1, 0, r4
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; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P9LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P9LE-NEXT: xvaddsp vs0, vs0, vs1
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; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 2
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; P9LE-NEXT: stfiwx f0, 0, r5
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; P9LE-NEXT: blr
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;
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; P9BE-LABEL: test_liwzx1:
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; P9BE: # %bb.0:
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; P9BE-NEXT: lfiwzx f0, 0, r3
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; P9BE-NEXT: lfiwzx f1, 0, r4
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; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P9BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P9BE-NEXT: xvaddsp vs0, vs0, vs1
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; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P9BE-NEXT: stfiwx f0, 0, r5
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; P9BE-NEXT: blr
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;
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; P8LE-LABEL: test_liwzx1:
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; P8LE: # %bb.0:
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; P8LE-NEXT: lfiwzx f0, 0, r3
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; P8LE-NEXT: lfiwzx f1, 0, r4
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; P8LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P8LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P8LE-NEXT: xvaddsp vs0, vs0, vs1
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; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 2
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; P8LE-NEXT: stfiwx f0, 0, r5
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; P8LE-NEXT: blr
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;
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; P8BE-LABEL: test_liwzx1:
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; P8BE: # %bb.0:
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; P8BE-NEXT: lfiwzx f0, 0, r3
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; P8BE-NEXT: lfiwzx f1, 0, r4
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P8BE-NEXT: xvaddsp vs0, vs0, vs1
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; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P8BE-NEXT: stfiwx f0, 0, r5
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; P8BE-NEXT: blr
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%a = load <1 x float>, <1 x float>* %A
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%b = load <1 x float>, <1 x float>* %B
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%X = fadd <1 x float> %a, %b
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store <1 x float> %X, <1 x float>* %C
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ret void
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}
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define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
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; P9LE-LABEL: test_liwzx2:
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; P9LE: # %bb.0:
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; P9LE-NEXT: lfiwzx f0, 0, r3
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; P9LE-NEXT: lfiwzx f1, 0, r4
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; P9LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P9LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P9LE-NEXT: xvsubsp vs0, vs0, vs1
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; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 2
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; P9LE-NEXT: mr r3, r5
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; P9LE-NEXT: stfiwx f0, 0, r5
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; P9LE-NEXT: blr
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;
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; P9BE-LABEL: test_liwzx2:
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; P9BE: # %bb.0:
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; P9BE-NEXT: lfiwzx f0, 0, r3
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; P9BE-NEXT: lfiwzx f1, 0, r4
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; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P9BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P9BE-NEXT: xvsubsp vs0, vs0, vs1
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; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P9BE-NEXT: mr r3, r5
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; P9BE-NEXT: stfiwx f0, 0, r5
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; P9BE-NEXT: blr
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;
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; P8LE-LABEL: test_liwzx2:
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; P8LE: # %bb.0:
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; P8LE-NEXT: lfiwzx f0, 0, r3
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; P8LE-NEXT: lfiwzx f1, 0, r4
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; P8LE-NEXT: mr r3, r5
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; P8LE-NEXT: xxpermdi vs0, f0, f0, 2
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; P8LE-NEXT: xxpermdi vs1, f1, f1, 2
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; P8LE-NEXT: xvsubsp vs0, vs0, vs1
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; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 2
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; P8LE-NEXT: stfiwx f0, 0, r5
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; P8LE-NEXT: blr
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;
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; P8BE-LABEL: test_liwzx2:
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; P8BE: # %bb.0:
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; P8BE-NEXT: lfiwzx f0, 0, r3
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; P8BE-NEXT: lfiwzx f1, 0, r4
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; P8BE-NEXT: mr r3, r5
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; P8BE-NEXT: xxsldwi vs0, f0, f0, 1
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; P8BE-NEXT: xxsldwi vs1, f1, f1, 1
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; P8BE-NEXT: xvsubsp vs0, vs0, vs1
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; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 3
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; P8BE-NEXT: stfiwx f0, 0, r5
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; P8BE-NEXT: blr
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%a = load <1 x float>, <1 x float>* %A
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%b = load <1 x float>, <1 x float>* %B
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%X = fsub <1 x float> %a, %b
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store <1 x float> %X, <1 x float>* %C
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ret <1 x float>* %C
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}
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