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2c9195363f
Store rlwinm Rx, Ry, 32, 0, 31 as rlwinm Rx, Ry, 0, 0, 31 and store rldicl Rx, Ry, 64, 0 as rldicl Rx, Ry, 0, 0. Otherwise SH field is overflow and fails assertion in assembly printing stage. Differential Revision: https://reviews.llvm.org/D66991 llvm-svn: 373519
59 lines
1.6 KiB
YAML
59 lines
1.6 KiB
YAML
# RUN: llc -O3 -mtriple=powerpc64le-unknown-linux-gnu -start-after ppc-mi-peepholes -ppc-late-peephole -ppc-asm-full-reg-names -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: special_right_shift32_0
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprc }
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- { id: 1, class: gprc }
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- { id: 2, class: gprc }
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liveins:
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- { reg: '$r3', virtual-reg: '%0' }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $r3
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; Ensure we do not attempt to transform this into srwi $r3, $r3, 0 in the
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; form specified by ISA 3.0b (rlwinm $r3, $r3, 32 - 0, 0, 31)
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; CHECK-LABEL: special_right_shift32_0:
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; CHECK: slwi r[[#]], r[[#]], 0
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%0:gprc = COPY killed $r3
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%1:gprc = LI 0
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%2:gprc = SRW killed %0, killed %1
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$r3 = COPY killed %2
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BLR implicit $lr, implicit $rm, implicit killed $r3
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...
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---
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name: special_right_shift64_0
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alignment: 2
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tracksRegLiveness: true
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registers:
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- { id: 0, class: g8rc }
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- { id: 1, class: gprc }
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- { id: 2, class: g8rc }
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liveins:
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- { reg: '$x3', virtual-reg: '%0' }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x3
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; Ensure we do not attempt to transform this into srdi $r3, $r3, 0 in the
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; form specified by ISA 3.0b (rldicl $r3, $r3, 64 - 0, 0)
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; CHECK-LABEL: special_right_shift64_0:
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; CHECK: rotldi r[[#]], r[[#]], 0
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%0:g8rc = COPY killed $x3
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%1:gprc = LI 0
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%2:g8rc = SRD killed %0, killed %1
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$x3 = COPY killed %2
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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...
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