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63c8cd21e5
Prefetches used to always be chained between any previous and following memory accesses. The problem with this was that later optimizations, such as folding of a load into the user instruction, got disrupted. This patch relaxes the chaining of prefetches in order to remedy this. Reveiw: Hal Finkel https://reviews.llvm.org/D38886 llvm-svn: 322163
87 lines
3.9 KiB
LLVM
87 lines
3.9 KiB
LLVM
; Test that selection of Vector Load Element instructions work in the presence of prefetches.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; CHECK-LABEL: .LBB0_1:
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; CHECK-NOT: l %r
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; CHECK-NOT: vlvgf
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; CHECK: pfd
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; CHECK: vlef
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%type0 = type { i32, [400 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
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@Mem = external global [150 x %type0], align 4
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define void @fun() local_unnamed_addr #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ 0, %entry ], [ %index.next.3, %vector.body ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %57, %vector.body ]
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%0 = or i64 %index, 2
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%1 = or i64 %index, 3
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%2 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 0, i32 3
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%3 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %0, i32 3
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%4 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %1, i32 3
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%5 = load i32, i32* null, align 4
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%6 = load i32, i32* %3, align 4
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%7 = load i32, i32* %4, align 4
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%8 = insertelement <4 x i32> undef, i32 %5, i32 0
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%9 = insertelement <4 x i32> %8, i32 0, i32 1
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%10 = insertelement <4 x i32> %9, i32 %6, i32 2
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%11 = insertelement <4 x i32> %10, i32 %7, i32 3
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%12 = add nsw <4 x i32> %11, %vec.phi
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%13 = or i64 %index, 7
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%14 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 undef, i32 3
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%15 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 0, i32 3
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%16 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %13, i32 3
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%17 = load i32, i32* %14, align 4
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%18 = load i32, i32* undef, align 4
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%19 = load i32, i32* %15, align 4
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%20 = load i32, i32* %16, align 4
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%21 = insertelement <4 x i32> undef, i32 %17, i32 0
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%22 = insertelement <4 x i32> %21, i32 %18, i32 1
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%23 = insertelement <4 x i32> %22, i32 %19, i32 2
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%24 = insertelement <4 x i32> %23, i32 %20, i32 3
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%25 = add nsw <4 x i32> %24, %12
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%26 = or i64 %index, 9
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%27 = or i64 %index, 10
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%28 = or i64 %index, 11
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%29 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 undef, i32 3
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%30 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %26, i32 3
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%31 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %27, i32 3
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%32 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %28, i32 3
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%33 = load i32, i32* %29, align 4
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%34 = load i32, i32* %30, align 4
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%35 = load i32, i32* %31, align 4
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%36 = load i32, i32* %32, align 4
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%37 = insertelement <4 x i32> undef, i32 %33, i32 0
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%38 = insertelement <4 x i32> %37, i32 %34, i32 1
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%39 = insertelement <4 x i32> %38, i32 %35, i32 2
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%40 = insertelement <4 x i32> %39, i32 %36, i32 3
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%41 = add nsw <4 x i32> %40, %25
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%42 = or i64 %index, 13
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%43 = or i64 %index, 14
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%44 = or i64 %index, 15
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%45 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 undef, i32 3
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%46 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %42, i32 3
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%47 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %43, i32 3
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%48 = getelementptr inbounds [150 x %type0], [150 x %type0]* @Mem, i64 0, i64 %44, i32 3
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%49 = load i32, i32* %45, align 4
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%50 = load i32, i32* %46, align 4
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%51 = load i32, i32* %47, align 4
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%52 = load i32, i32* %48, align 4
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%53 = insertelement <4 x i32> undef, i32 %49, i32 0
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%54 = insertelement <4 x i32> %53, i32 %50, i32 1
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%55 = insertelement <4 x i32> %54, i32 %51, i32 2
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%56 = insertelement <4 x i32> %55, i32 %52, i32 3
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%57 = add nsw <4 x i32> %56, %41
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%index.next.3 = add i64 %index, 16
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br i1 false, label %middle.block.unr-lcssa, label %vector.body
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middle.block.unr-lcssa: ; preds = %vector.body
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%rdx.shuf = shufflevector <4 x i32> %57, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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unreachable
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}
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