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207bf131ca
This patch fixes two deficiencies in current code that recognizes the VLLEZ idiom: - For the floating-point versions, we have ISel patterns that match on a bitconvert as the top node. In more complex cases, that bitconvert may already have been merged into something else. Fix the patterns to match the inner nodes instead. - For the 64-bit integer versions, depending on the surrounding code, we may get either a DAG tree based on JOIN_DWORDS or one based on INSERT_VECTOR_ELT. Use a PatFrags to simply match both variants. llvm-svn: 349749
37 lines
999 B
LLVM
37 lines
999 B
LLVM
; Test insertions of memory values into 0 on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test VLLEZLF.
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define <4 x i32> @f1(i32 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vllezlf %v24, 0(%r2)
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; CHECK: br %r14
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%val = load i32, i32 *%ptr
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%ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 0
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ret <4 x i32> %ret
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}
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; Test VLLEZLF with a float.
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define <4 x float> @f2(float *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vllezlf %v24, 0(%r2)
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; CHECK: br %r14
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%val = load float, float *%ptr
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%ret = insertelement <4 x float> zeroinitializer, float %val, i32 0
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ret <4 x float> %ret
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}
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; Test VLLEZLF with a float when the result is stored to memory.
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define void @f3(float *%ptr, <4 x float> *%res) {
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; CHECK-LABEL: f3:
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; CHECK: vllezlf [[REG:%v[0-9]+]], 0(%r2)
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; CHECK: vst [[REG]], 0(%r3)
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; CHECK: br %r14
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%val = load float, float *%ptr
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%ret = insertelement <4 x float> zeroinitializer, float %val, i32 0
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store <4 x float> %ret, <4 x float> *%res
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ret void
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}
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