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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
23 lines
771 B
LLVM
23 lines
771 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,-slow-unaligned-mem-32 | FileCheck %s --check-prefix=FAST
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+slow-unaligned-mem-32 | FileCheck %s --check-prefix=SLOW
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define i256 @foo(<8 x i32> %a) {
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; FAST-LABEL: foo:
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; FAST: # %bb.0:
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; FAST-NEXT: movq %rdi, %rax
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; FAST-NEXT: vmovups %ymm0, (%rdi)
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; FAST-NEXT: vzeroupper
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; FAST-NEXT: retq
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;
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; SLOW-LABEL: foo:
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; SLOW: # %bb.0:
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; SLOW-NEXT: movq %rdi, %rax
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; SLOW-NEXT: vextractf128 $1, %ymm0, 16(%rdi)
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; SLOW-NEXT: vmovups %xmm0, (%rdi)
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; SLOW-NEXT: vzeroupper
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; SLOW-NEXT: retq
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%r = bitcast <8 x i32> %a to i256
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ret i256 %r
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}
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