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https://github.com/RPCS3/llvm-mirror.git
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185 lines
5.8 KiB
LLVM
185 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
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declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
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declare {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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; fold (ssub x, 0) -> x
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define i32 @combine_ssub_zero(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_ssub_zero:
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; SSE: # %bb.0:
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; SSE-NEXT: movl %edi, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_ssub_zero:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 zeroinitializer)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_ssub_zero(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_ssub_zero:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_ssub_zero:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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; fold (usub x, 0) -> x
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define i32 @combine_usub_zero(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_usub_zero:
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; SSE: # %bb.0:
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; SSE-NEXT: movl %edi, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_usub_zero:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a0, i32 zeroinitializer)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_usub_zero(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_usub_zero:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_usub_zero:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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; fold (ssub x, x) -> 0
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define i32 @combine_ssub_self(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_ssub_self:
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; SSE: # %bb.0:
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; SSE-NEXT: xorl %eax, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_ssub_self:
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; AVX: # %bb.0:
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 %a0)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_ssub_self(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_ssub_self:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_ssub_self:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a0)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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; fold (usub x, x) -> x
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define i32 @combine_usub_self(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_usub_self:
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; SSE: # %bb.0:
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; SSE-NEXT: xorl %eax, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_usub_self:
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; AVX: # %bb.0:
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a0, i32 %a0)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_usub_self(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_usub_self:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_usub_self:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a0)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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; fold (usub -1, x) -> (xor x, -1) + no borrow
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define i32 @combine_usub_negone(i32 %a0, i32 %a1) {
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; SSE-LABEL: combine_usub_negone:
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; SSE: # %bb.0:
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; SSE-NEXT: movl %edi, %eax
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; SSE-NEXT: notl %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_usub_negone:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: notl %eax
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; AVX-NEXT: retq
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%1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -1, i32 %a0)
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%2 = extractvalue {i32, i1} %1, 0
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%3 = extractvalue {i32, i1} %1, 1
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%4 = select i1 %3, i32 %a1, i32 %2
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ret i32 %4
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}
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define <4 x i32> @combine_vec_usub_negone(<4 x i32> %a0, <4 x i32> %a1) {
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; SSE-LABEL: combine_vec_usub_negone:
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; SSE: # %bb.0:
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; SSE-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_usub_negone:
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; AVX: # %bb.0:
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; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %a0)
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%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
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%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
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%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
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ret <4 x i32> %4
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}
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