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15bccaadfa
This is another step towards ensuring that we produce the optimal code for reductions, but there are other potential benefits as seen in the tests diffs: 1. Memory loads may get scalarized resulting in more efficient code. 2. Memory stores may get scalarized resulting in more efficient code. 3. Complex ops like fdiv/sqrt get scalarized which may be faster instructions depending on uarch. 4. Even simple ops like addss/subss/mulss/roundss may result in faster operation/less frequency throttling when scalarized depending on uarch. The TODO comment suggests 1 or more follow-ups for opcodes that can currently result in regressions. Differential Revision: https://reviews.llvm.org/D58282 llvm-svn: 355130
88 lines
2.5 KiB
LLVM
88 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
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; Verify that we select the correct version of the instruction that stores the low 64-bits
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; of a 128-bit vector. We want to avoid int/fp domain crossing penalties, so ignore the
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; bitcast ops and choose:
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;
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; movlps for floats
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; movlpd for doubles
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; movq for integers
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define void @store_floats(<4 x float> %x, i64* %p) {
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; SSE-LABEL: store_floats:
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; SSE: # %bb.0:
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; SSE-NEXT: addps %xmm0, %xmm0
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; SSE-NEXT: movlps %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_floats:
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; AVX: # %bb.0:
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; AVX-NEXT: vaddps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovlps %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = fadd <4 x float> %x, %x
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%b = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%c = bitcast <2 x float> %b to i64
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store i64 %c, i64* %p
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ret void
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}
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define void @store_double(<2 x double> %x, i64* %p) {
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; SSE-LABEL: store_double:
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; SSE: # %bb.0:
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; SSE-NEXT: addsd %xmm0, %xmm0
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; SSE-NEXT: movsd %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_double:
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; AVX: # %bb.0:
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; AVX-NEXT: vaddsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovsd %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = fadd <2 x double> %x, %x
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%b = extractelement <2 x double> %a, i32 0
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%c = bitcast double %b to i64
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store i64 %c, i64* %p
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ret void
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}
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define void @store_int(<4 x i32> %x, <2 x float>* %p) {
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; SSE-LABEL: store_int:
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; SSE: # %bb.0:
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; SSE-NEXT: paddd %xmm0, %xmm0
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; SSE-NEXT: movq %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_int:
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; AVX: # %bb.0:
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; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovq %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = add <4 x i32> %x, %x
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%c = bitcast <2 x i32> %b to <2 x float>
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store <2 x float> %c, <2 x float>* %p
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ret void
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}
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define void @store_h_double(<2 x double> %x, i64* %p) {
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; SSE-LABEL: store_h_double:
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; SSE: # %bb.0:
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; SSE-NEXT: addpd %xmm0, %xmm0
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; SSE-NEXT: movhpd %xmm0, (%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: store_h_double:
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; AVX: # %bb.0:
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; AVX-NEXT: vaddpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vmovhpd %xmm0, (%rdi)
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; AVX-NEXT: retq
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%a = fadd <2 x double> %x, %x
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%b = extractelement <2 x double> %a, i32 1
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%c = bitcast double %b to i64
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store i64 %c, i64* %p
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ret void
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}
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