mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
60e9ada729
The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
36 lines
853 B
LLVM
36 lines
853 B
LLVM
; RUN: llc -march=x86-64 < %s | FileCheck %s
|
|
@sc8 = external global i8
|
|
|
|
define void @atomic_maxmin_i8() {
|
|
; CHECK: atomic_maxmin_i8
|
|
%1 = atomicrmw max i8* @sc8, i8 5 acquire
|
|
; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]:
|
|
; CHECK: movsbl
|
|
; CHECK: cmpl
|
|
; CHECK: lock
|
|
; CHECK-NEXT: cmpxchgb
|
|
; CHECK: jne [[LABEL1]]
|
|
%2 = atomicrmw min i8* @sc8, i8 6 acquire
|
|
; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]:
|
|
; CHECK: movsbl
|
|
; CHECK: cmpl
|
|
; CHECK: lock
|
|
; CHECK-NEXT: cmpxchgb
|
|
; CHECK: jne [[LABEL3]]
|
|
%3 = atomicrmw umax i8* @sc8, i8 7 acquire
|
|
; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]:
|
|
; CHECK: movzbl
|
|
; CHECK: cmpl
|
|
; CHECK: lock
|
|
; CHECK-NEXT: cmpxchgb
|
|
; CHECK: jne [[LABEL5]]
|
|
%4 = atomicrmw umin i8* @sc8, i8 8 acquire
|
|
; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]:
|
|
; CHECK: movzbl
|
|
; CHECK: cmpl
|
|
; CHECK: lock
|
|
; CHECK-NEXT: cmpxchgb
|
|
; CHECK: jne [[LABEL7]]
|
|
ret void
|
|
}
|