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e0801b07e0
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
98 lines
3.3 KiB
C++
98 lines
3.3 KiB
C++
//===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the x86
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// target library, as used by the LLVM JIT.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_X86_H
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#define TARGET_X86_H
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class JITCodeEmitter;
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class MCCodeEmitter;
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class MCContext;
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class MCObjectWriter;
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class MachineCodeEmitter;
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class Target;
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class TargetAsmBackend;
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class X86TargetMachine;
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class formatted_raw_ostream;
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class raw_ostream;
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/// createX86ISelDag - This pass converts a legalized DAG into a
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/// X86-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *createX86ISelDag(X86TargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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/// createGlobalBaseRegPass - This pass initializes a global base
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/// register for PIC on x86-32.
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FunctionPass* createGlobalBaseRegPass();
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/// createX86FloatingPointStackifierPass - This function returns a pass which
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/// converts floating point register references and pseudo instructions into
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/// floating point stack references and physical instructions.
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///
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FunctionPass *createX86FloatingPointStackifierPass();
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/// createSSEDomainFixPass - This pass twiddles SSE opcodes to prevent domain
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/// crossings.
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FunctionPass *createSSEDomainFixPass();
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/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
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/// to the specified MCE object.
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FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
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JITCodeEmitter &JCE);
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MCCodeEmitter *createX86_32MCCodeEmitter(const Target &, TargetMachine &TM,
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MCContext &Ctx);
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MCCodeEmitter *createX86_64MCCodeEmitter(const Target &, TargetMachine &TM,
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MCContext &Ctx);
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TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &);
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TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &);
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/// createX86EmitCodeToMemory - Returns a pass that converts a register
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/// allocated function into raw machine code in a dynamically
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/// allocated chunk of memory.
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///
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FunctionPass *createEmitX86CodeToMemory();
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/// createX86MaxStackAlignmentHeuristicPass - This function returns a pass
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/// which determines whether the frame pointer register should be
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/// reserved in case dynamic stack alignment is later required.
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///
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FunctionPass *createX86MaxStackAlignmentHeuristicPass();
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/// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
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MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
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bool Is64Bit,
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uint32_t CPUType,
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uint32_t CPUSubtype);
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extern Target TheX86_32Target, TheX86_64Target;
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} // End llvm namespace
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#include "TargetDesc/X86TargetDesc.h"
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// Defines symbolic names for the X86 instructions.
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//
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#include "X86GenInstrNames.inc"
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#endif
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