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686f12811b
We need to make sure that we are sensibly dealing with vectors of types v2i64 and v2f64, even if most of the time we cannot generate native operations for them. This mostly adds a lot of testing, plus fixes up a couple of the issues found. And, or and xor can be legal for v2i64, and shifts combining needs a slight fixup. Differential Revision: https://reviews.llvm.org/D64316 llvm-svn: 366106
141 lines
3.7 KiB
LLVM
141 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <8 x i16> @sext_v8i8_v8i16(<8 x i8> %src) {
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; CHECK-LABEL: sext_v8i8_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sext <8 x i8> %src to <8 x i16>
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_v4i16_v4i32(<4 x i16> %src) {
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; CHECK-LABEL: sext_v4i16_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sext <4 x i16> %src to <4 x i32>
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_v4i8_v4i32(<4 x i8> %src) {
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; CHECK-LABEL: sext_v4i8_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sext <4 x i8> %src to <4 x i32>
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @sext_v2i32_v2i64(<2 x i32> %src) {
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; CHECK-LABEL: sext_v2i32_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s0
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; CHECK-NEXT: vmov.32 q1[0], r0
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; CHECK-NEXT: asrs r0, r0, #31
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; CHECK-NEXT: vmov.32 q1[1], r0
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; CHECK-NEXT: vmov r0, s2
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; CHECK-NEXT: vmov.32 q1[2], r0
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; CHECK-NEXT: asrs r0, r0, #31
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; CHECK-NEXT: vmov.32 q1[3], r0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = sext <2 x i32> %src to <2 x i64>
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_v8i8_v8i16(<8 x i8> %src) {
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; CHECK-LABEL: zext_v8i8_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext <8 x i8> %src to <8 x i16>
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_v4i16_v4i32(<4 x i16> %src) {
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; CHECK-LABEL: zext_v4i16_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext <4 x i16> %src to <4 x i32>
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_v4i8_v4i32(<4 x i8> %src) {
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; CHECK-LABEL: zext_v4i8_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.i32 q1, #0xff
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext <4 x i8> %src to <4 x i32>
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @zext_v2i32_v2i64(<2 x i32> %src) {
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; CHECK-LABEL: zext_v2i32_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: adr r0, .LCPI7_0
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI7_0:
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 0 @ 0x0
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entry:
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%0 = zext <2 x i32> %src to <2 x i64>
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <8 x i8> @trunc_v8i16_v8i8(<8 x i16> %src) {
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; CHECK-LABEL: trunc_v8i16_v8i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <8 x i16> %src to <8 x i8>
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ret <8 x i8> %0
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}
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define arm_aapcs_vfpcc <4 x i16> @trunc_v4i32_v4i16(<4 x i32> %src) {
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; CHECK-LABEL: trunc_v4i32_v4i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <4 x i32> %src to <4 x i16>
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ret <4 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i8> @trunc_v4i32_v4i8(<4 x i32> %src) {
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; CHECK-LABEL: trunc_v4i32_v4i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <4 x i32> %src to <4 x i8>
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ret <4 x i8> %0
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}
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define arm_aapcs_vfpcc <2 x i32> @trunc_v2i64_v2i32(<2 x i64> %src) {
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; CHECK-LABEL: trunc_v2i64_v2i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%0 = trunc <2 x i64> %src to <2 x i32>
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ret <2 x i32> %0
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}
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