Sanjay Patel 8830999b87 [DAGCombine] Prevent the transform of combine for multi-use operand ... The test is based on a miscompile example in: https://llvm.org/PR51321 Differential Revision: https://reviews.llvm.org/D107692 (cherry picked from commit e1e4bf174b09bcd4b25cd624f177537890bff785)		2021-09-07 22:33:53 -07:00
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CMakeLists.txt
DAGCombiner.cpp	[DAGCombine] Prevent the transform of combine for multi-use operand	2021-09-07 22:33:53 -07:00
FastISel.cpp	[InstrRef][FastISel] Support emitting DBG_INSTR_REF from fast-isel	2021-07-16 13:56:15 +01:00
FunctionLoweringInfo.cpp
InstrEmitter.cpp	[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations	2021-07-06 18:31:38 +01:00
InstrEmitter.h	[DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations	2021-07-06 18:31:38 +01:00
LegalizeDAG.cpp	[TargetLowering][AArch64][SVE] Take into account accessed type when clamping address	2021-06-30 13:30:18 +01:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	[SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero	2021-08-31 20:59:28 -07:00
LegalizeTypes.cpp
LegalizeTypes.h	[SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets.	2021-07-12 14:53:42 -07:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp	[AArch64][SVE] Add support for fixed length MSCATTER/MGATHER	2021-07-01 12:13:59 +01:00
LegalizeVectorTypes.cpp	[llvm] Add enum iteration to Sequence	2021-07-21 12:48:53 +00:00
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h
SelectionDAG.cpp	[SelectionDAG] Support scalable-vector splats in yet more cases	2021-07-26 10:15:08 +01:00
SelectionDAGAddressAnalysis.cpp
SelectionDAGBuilder.cpp	[AArch64] Legalize MVT::i64x8 in DAG isel lowering	2021-08-02 15:45:58 +01:00
SelectionDAGBuilder.h
SelectionDAGDumper.cpp	[ISel] Port AArch64 SABD and UABD to DAGCombine	2021-06-26 19:34:16 +01:00
SelectionDAGISel.cpp	[DebugInfo][InstrRef] Don't break up ret-sequences on debug-info instrs	2021-07-29 15:08:13 +01:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp
StatepointLowering.h
TargetLowering.cpp	[SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero	2021-08-31 20:59:28 -07:00