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51b479815c
This is required in order to determine during disassembly whether a Reg bead without associated DA bead is referring to a data register. Differential Revision: https://reviews.llvm.org/D98534
93 lines
3.5 KiB
TableGen
93 lines
3.5 KiB
TableGen
//===------ M68kInstrShiftRotate.td - Logical Instrs -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file describes the logical instructions in the M68k architecture.
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/// Here is the current status of the file:
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///
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/// Machine:
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///
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/// SHL [~] ASR [~] LSR [~] SWAP [ ]
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/// ROL [~] ROR [~] ROXL [ ] ROXR [ ]
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///
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/// Map:
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///
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/// [ ] - was not touched at all
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/// [!] - requires extarnal stuff implemented
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/// [~] - in progress but usable
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/// [x] - done
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///
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//===----------------------------------------------------------------------===//
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def MxRODI_R : MxBead1Bit<0>;
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def MxRODI_L : MxBead1Bit<1>;
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def MxROOP_AS : MxBead2Bits<0b00>;
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def MxROOP_LS : MxBead2Bits<0b01>;
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def MxROOP_ROX : MxBead2Bits<0b10>;
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def MxROOP_RO : MxBead2Bits<0b11>;
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/// ------------+---------+---+------+---+------+---------
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/// F E D C | B A 9 | 8 | 7 6 | 5 | 4 3 | 2 1 0
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/// ------------+---------+---+------+---+------+---------
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/// 1 1 1 0 | REG/IMM | D | SIZE |R/I| OP | REG
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/// ------------+---------+---+------+---+------+---------
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class MxSREncoding_R<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
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: MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<1>, SIZE, DIRECTION,
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MxBeadDReg<2>, MxBead4Bits<0b1110>>;
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class MxSREncoding_I<MxBead1Bit DIRECTION, MxBead2Bits ROOP, MxEncSize SIZE>
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: MxEncoding<MxBeadDReg<0>, ROOP, MxBead1Bit<0>, SIZE, DIRECTION,
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MxBead3Imm<2, 1>, MxBead4Bits<0b1110>>;
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// $reg <- $reg op $reg
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class MxSR_DD<string MN, MxType TYPE, SDNode NODE,
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MxBead1Bit RODI, MxBead2Bits ROOP>
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: MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src, TYPE.ROp:$opd),
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MN#"."#TYPE.Prefix#"\t$opd, $dst",
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[(set TYPE.VT:$dst, (NODE TYPE.VT:$src, TYPE.VT:$opd))],
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MxSREncoding_R<RODI, ROOP,
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!cast<MxEncSize>("MxEncSize"#TYPE.Size)>>;
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// $reg <- $reg op $imm
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class MxSR_DI<string MN, MxType TYPE, SDNode NODE,
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MxBead1Bit RODI, MxBead2Bits ROOP>
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: MxInst<(outs TYPE.ROp:$dst),
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(ins TYPE.ROp:$src, !cast<Operand>("Mxi"#TYPE.Size#"imm"):$opd),
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MN#"."#TYPE.Prefix#"\t$opd, $dst",
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[(set TYPE.VT:$dst,
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(NODE TYPE.VT:$src,
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!cast<ImmLeaf>("Mximm"#TYPE.Size#"_1to8"):$opd))],
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MxSREncoding_I<RODI, ROOP,
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!cast<MxEncSize>("MxEncSize"#TYPE.Size)>>;
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multiclass MxSROp<string MN, SDNode NODE, MxBead1Bit RODI, MxBead2Bits ROOP> {
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let Defs = [CCR] in {
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let Constraints = "$src = $dst" in {
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def NAME#"8dd" : MxSR_DD<MN, MxType8d, NODE, RODI, ROOP>;
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def NAME#"16dd" : MxSR_DD<MN, MxType16d, NODE, RODI, ROOP>;
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def NAME#"32dd" : MxSR_DD<MN, MxType32d, NODE, RODI, ROOP>;
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def NAME#"8di" : MxSR_DI<MN, MxType8d, NODE, RODI, ROOP>;
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def NAME#"16di" : MxSR_DI<MN, MxType16d, NODE, RODI, ROOP>;
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def NAME#"32di" : MxSR_DI<MN, MxType32d, NODE, RODI, ROOP>;
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} // $src = $dst
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} // Defs = [CCR]
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} // MxBiArOp_RF
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defm SHL : MxSROp<"lsl", shl, MxRODI_L, MxROOP_LS>;
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defm LSR : MxSROp<"lsr", srl, MxRODI_R, MxROOP_LS>;
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defm ASR : MxSROp<"asr", sra, MxRODI_R, MxROOP_AS>;
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defm ROL : MxSROp<"rol", rotl, MxRODI_L, MxROOP_RO>;
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defm ROR : MxSROp<"ror", rotr, MxRODI_R, MxROOP_RO>;
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