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7ebfc5f86b
This patch corresponds to review: The newly added VSX D-Form (register + offset) memory ops target the upper half of the VSX register set. The existing ones target the lower half. In order to unify these and have the ability to target all the VSX registers using D-Form operations, this patch defines Pseudo-ops for the loads/stores which are expanded post-RA. The expansion then choses the correct opcode based on the register that was allocated for the operation. llvm-svn: 283212
172 lines
3.6 KiB
LLVM
172 lines
3.6 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=a2 | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=g5
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck -check-prefix=CHECK-P9 %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i64 @foo(float %a) nounwind {
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%x = fptosi float %a to i64
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ret i64 %x
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; CHECK: @foo
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; CHECK: fctidz [[REG:[0-9]+]], 1
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; CHECK: stfd [[REG]],
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; CHECK: ld 3,
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; CHECK: blr
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; CHECK-VSX: @foo
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; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
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; CHECK-VSX: stxsdx [[REG]],
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; CHECK-VSX: ld 3,
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; CHECK-VSX: blr
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; CHECK-LABEL-P9: @foo
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; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
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; CHECK-P9: stfd [[REG]],
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; CHECK-P9: ld 3,
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; CHECK-P9: blr
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}
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define i64 @foo2(double %a) nounwind {
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%x = fptosi double %a to i64
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ret i64 %x
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; CHECK: @foo2
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; CHECK: fctidz [[REG:[0-9]+]], 1
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; CHECK: stfd [[REG]],
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; CHECK: ld 3,
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; CHECK: blr
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; CHECK-VSX: @foo2
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; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
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; CHECK-VSX: stxsdx [[REG]],
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; CHECK-VSX: ld 3,
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; CHECK-VSX: blr
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; CHECK-LABEL-P9: @foo2
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; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 1
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; CHECK-P9: stfd [[REG]],
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; CHECK-P9: ld 3,
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; CHECK-P9: blr
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}
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define i64 @foo3(float %a) nounwind {
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%x = fptoui float %a to i64
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ret i64 %x
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; CHECK: @foo3
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; CHECK: fctiduz [[REG:[0-9]+]], 1
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; CHECK: stfd [[REG]],
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; CHECK: ld 3,
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; CHECK: blr
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; CHECK-VSX: @foo3
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; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
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; CHECK-VSX: stxsdx [[REG]],
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; CHECK-VSX: ld 3,
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; CHECK-VSX: blr
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; CHECK-LABEL-P9: @foo3
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; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
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; CHECK-P9: stfd [[REG]],
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; CHECK-P9: ld 3,
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; CHECK-P9: blr
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}
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define i64 @foo4(double %a) nounwind {
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%x = fptoui double %a to i64
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ret i64 %x
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; CHECK: @foo4
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; CHECK: fctiduz [[REG:[0-9]+]], 1
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; CHECK: stfd [[REG]],
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; CHECK: ld 3,
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; CHECK: blr
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; CHECK-VSX: @foo4
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; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
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; CHECK-VSX: stxsdx [[REG]],
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; CHECK-VSX: ld 3,
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; CHECK-VSX: blr
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; CHECK-LABEL-P9: @foo4
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; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 1
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; CHECK-P9: stfd [[REG]],
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; CHECK-P9: ld 3,
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; CHECK-P9: blr
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}
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define i32 @goo(float %a) nounwind {
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%x = fptosi float %a to i32
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ret i32 %x
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; CHECK: @goo
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; CHECK: fctiwz [[REG:[0-9]+]], 1
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; CHECK: stfiwx [[REG]],
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; CHECK: lwz 3,
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; CHECK: blr
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; CHECK-VSX: @goo
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; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1
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; CHECK-VSX: stfiwx [[REG]],
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; CHECK-VSX: lwz 3,
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; CHECK-VSX: blr
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}
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define i32 @goo2(double %a) nounwind {
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%x = fptosi double %a to i32
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ret i32 %x
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; CHECK: @goo2
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; CHECK: fctiwz [[REG:[0-9]+]], 1
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; CHECK: stfiwx [[REG]],
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; CHECK: lwz 3,
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; CHECK: blr
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; CHECK-VSX: @goo2
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; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1
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; CHECK-VSX: stfiwx [[REG]],
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; CHECK-VSX: lwz 3,
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; CHECK-VSX: blr
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}
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define i32 @goo3(float %a) nounwind {
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%x = fptoui float %a to i32
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ret i32 %x
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; CHECK: @goo3
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; CHECK: fctiwuz [[REG:[0-9]+]], 1
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; CHECK: stfiwx [[REG]],
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; CHECK: lwz 3,
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; CHECK: blr
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; CHECK-VSX: @goo3
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; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1
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; CHECK-VSX: stfiwx [[REG]],
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; CHECK-VSX: lwz 3,
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; CHECK-VSX: blr
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}
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define i32 @goo4(double %a) nounwind {
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%x = fptoui double %a to i32
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ret i32 %x
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; CHECK: @goo4
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; CHECK: fctiwuz [[REG:[0-9]+]], 1
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; CHECK: stfiwx [[REG]],
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; CHECK: lwz 3,
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; CHECK: blr
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; CHECK-VSX: @goo4
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; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1
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; CHECK-VSX: stfiwx [[REG]],
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; CHECK-VSX: lwz 3,
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; CHECK-VSX: blr
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}
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