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45b647d5eb
This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
133 lines
4.4 KiB
C++
133 lines
4.4 KiB
C++
//===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXRegisterInfo.h"
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#include "NVPTX.h"
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#include "NVPTXSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/MC/MachineLocation.h"
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using namespace llvm;
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#define DEBUG_TYPE "nvptx-reg-info"
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namespace llvm {
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std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
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if (RC == &NVPTX::Float32RegsRegClass)
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return ".f32";
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if (RC == &NVPTX::Float16RegsRegClass)
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// Ideally fp16 registers should be .f16, but this syntax is only
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// supported on sm_53+. On the other hand, .b16 registers are
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// accepted for all supported fp16 instructions on all GPU
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// variants, so we can use them instead.
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return ".b16";
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if (RC == &NVPTX::Float16x2RegsRegClass)
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return ".b32";
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if (RC == &NVPTX::Float64RegsRegClass)
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return ".f64";
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if (RC == &NVPTX::Int64RegsRegClass)
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// We use untyped (.b) integer registers here as NVCC does.
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// Correctness of generated code does not depend on register type,
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// but using .s/.u registers runs into ptxas bug that prevents
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// assembly of otherwise valid PTX into SASS. Despite PTX ISA
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// specifying only argument size for fp16 instructions, ptxas does
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// not allow using .s16 or .u16 arguments for .fp16
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// instructions. At the same time it allows using .s32/.u32
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// arguments for .fp16v2 instructions:
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//
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// .reg .b16 rb16
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// .reg .s16 rs16
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// add.f16 rb16,rb16,rb16; // OK
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// add.f16 rs16,rs16,rs16; // Arguments mismatch for instruction 'add'
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// but:
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// .reg .b32 rb32
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// .reg .s32 rs32
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// add.f16v2 rb32,rb32,rb32; // OK
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// add.f16v2 rs32,rs32,rs32; // OK
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return ".b64";
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if (RC == &NVPTX::Int32RegsRegClass)
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return ".b32";
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if (RC == &NVPTX::Int16RegsRegClass)
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return ".b16";
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if (RC == &NVPTX::Int1RegsRegClass)
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return ".pred";
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if (RC == &NVPTX::SpecialRegsRegClass)
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return "!Special!";
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return "INTERNAL";
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}
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std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
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if (RC == &NVPTX::Float32RegsRegClass)
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return "%f";
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if (RC == &NVPTX::Float16RegsRegClass)
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return "%h";
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if (RC == &NVPTX::Float16x2RegsRegClass)
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return "%hh";
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if (RC == &NVPTX::Float64RegsRegClass)
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return "%fd";
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if (RC == &NVPTX::Int64RegsRegClass)
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return "%rd";
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if (RC == &NVPTX::Int32RegsRegClass)
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return "%r";
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if (RC == &NVPTX::Int16RegsRegClass)
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return "%rs";
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if (RC == &NVPTX::Int1RegsRegClass)
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return "%p";
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if (RC == &NVPTX::SpecialRegsRegClass)
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return "!Special!";
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return "INTERNAL";
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}
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}
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NVPTXRegisterInfo::NVPTXRegisterInfo() : NVPTXGenRegisterInfo(0) {}
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#define GET_REGINFO_TARGET_DESC
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#include "NVPTXGenRegisterInfo.inc"
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/// NVPTX Callee Saved Registers
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const MCPhysReg *
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NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
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static const MCPhysReg CalleeSavedRegs[] = { 0 };
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return CalleeSavedRegs;
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}
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BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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return Reserved;
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}
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void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
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MI.getOperand(FIOperandNum + 1).getImm();
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// Using I0 as the frame pointer
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MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return NVPTX::VRFrame;
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}
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