1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
llvm-mirror/test/CodeGen/ARM/ldst-f32-2-i32.ll
Evan Cheng c7ce7e2ac3 Given a pair of floating point load and store, if there are no other uses of
the load, then it may be legal to transform the load and store to integer
load and store of the same width.

This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []

to

ldr r12, []
str r12, []

rdar://8944252

llvm-svn: 124708
2011-02-02 01:06:55 +00:00

29 lines
910 B
LLVM

; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
; Check if the f32 load / store pair are optimized to i32 load / store.
; rdar://8944252
define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
; CHECK: t:
entry:
%src6 = bitcast float* %src to i8*
%0 = icmp eq i32 %width, 0
br i1 %0, label %return, label %bb
bb:
; CHECK: ldr [[REGISTER:(r[0-9]+)]], [r1], r3
; CHECK: str [[REGISTER]], [r2], #4
%j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
%tmp = mul i32 %j.05, %index
%uglygep = getelementptr i8* %src6, i32 %tmp
%src_addr.04 = bitcast i8* %uglygep to float*
%dst_addr.03 = getelementptr float* %dst, i32 %j.05
%1 = load float* %src_addr.04, align 4
store float %1, float* %dst_addr.03, align 4
%2 = add i32 %j.05, 1
%exitcond = icmp eq i32 %2, %width
br i1 %exitcond, label %return, label %bb
return:
ret void
}