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ac6d037b49
This commit adds a ManglingOptions struct to IRMaterializationUnit, and replaces IRCompileLayer::CompileFunction with a new IRCompileLayer::IRCompiler class. The ManglingOptions struct defines the emulated-TLS state (via a bool member, EmulatedTLS, which is true if emulated-TLS is enabled and false otherwise). The IRCompileLayer::IRCompiler class wraps an IRCompiler (the same way that the CompileFunction typedef used to), but adds a method to return the IRCompileLayer::ManglingOptions that the compiler will use. These changes allow us to correctly determine the symbols that will be produced when a thread local global variable defined at the IR level is compiled with or without emulated TLS. This is required for ORCv2, where MaterializationUnits must declare their interface up-front. Most ORCv2 clients should not require any changes. Clients writing custom IR compilers will need to wrap their compiler in an IRCompileLayer::IRCompiler, rather than an IRCompileLayer::CompileFunction, however this should be a straightforward change (see modifications to CompileUtils.* in this patch for an example).
24 lines
972 B
LLVM
24 lines
972 B
LLVM
; RUN: not lli -no-process-syms -emulated-tls -jit-kind=orc-lazy %s 2>&1 \
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; RUN: | FileCheck %s
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;
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; Test that emulated-tls does not generate any unexpected errors.
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;
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; Unfortunately we cannot test successful execution of JIT'd code with
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; emulated-tls as this would require the JIT itself, in this case lli, to be
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; built with emulated-tls, which is not a common configuration. Instead we test
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; that the only error produced by the JIT for a thread-local with emulated-tls
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; enabled is a missing symbol error for __emutls_get_address. An unresolved
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; reference to this symbol (and only this symbol) implies (1) that the emulated
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; tls lowering was applied, and (2) that thread locals defined in the JIT'd code
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; were otherwise handled correctly.
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; CHECK: JIT session error: Symbols not found: [ {{[^,]*}}__emutls_get_address ]
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@x = thread_local global i32 42, align 4
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define i32 @main(i32 %argc, i8** %argv) {
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entry:
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%0 = load i32, i32* @x, align 4
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ret i32 %0
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}
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