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llvm-mirror/lib/Target/RISCV
Matthias Braun e1c491ab05 TargetMachine: Merge TargetMachine and LLVMTargetMachine
Merge LLVMTargetMachine into TargetMachine.

- There is no in-tree target anymore that just implements TargetMachine
  but not LLVMTargetMachine.
- It should still be possible to stub out all the various functions in
  case a target does not want to use lib/CodeGen
- This simplifies the code and avoids methods ending up in the wrong
  interface.

Differential Revision: https://reviews.llvm.org/D38489

llvm-svn: 315633
2017-10-12 22:28:54 +00:00
..
AsmParser [Asm] Add debug tracing in table-generated assembly matcher 2017-10-11 09:17:43 +00:00
Disassembler [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
InstPrinter [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
MCTargetDesc [RISCV] Fix build after r315327 2017-10-11 12:09:06 +00:00
TargetInfo [RISCV] Add bare-bones RISC-V MCTargetDesc 2016-11-01 23:47:30 +00:00
CMakeLists.txt [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
LLVMBuild.txt [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
RISCV.td [RISCV] Add basic RISCVAsmParser 2017-08-08 14:32:35 +00:00
RISCVInstrFormats.td [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVInstrInfo.td [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVRegisterInfo.td
RISCVTargetMachine.cpp TargetMachine: Merge TargetMachine and LLVMTargetMachine 2017-10-12 22:28:54 +00:00
RISCVTargetMachine.h TargetMachine: Merge TargetMachine and LLVMTargetMachine 2017-10-12 22:28:54 +00:00