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119 lines
4.2 KiB
C++
119 lines
4.2 KiB
C++
//==--- llvm/CodeGen/ReachingDefAnalysis.h - Reaching Def Analysis -*- C++ -*---==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Reaching Defs Analysis pass.
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///
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/// This pass tracks for each instruction what is the “closest” reaching def of
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/// a given register. It is used by BreakFalseDeps (for clearance calculation)
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/// and ExecutionDomainFix (for arbitrating conflicting domains).
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///
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/// Note that this is different from the usual definition notion of liveness.
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/// The CPU doesn't care whether or not we consider a register killed.
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///
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_REACHINGDEFSANALYSIS_H
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#define LLVM_CODEGEN_REACHINGDEFSANALYSIS_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LoopTraversal.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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namespace llvm {
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class MachineBasicBlock;
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class MachineInstr;
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/// This class provides the reaching def analysis.
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class ReachingDefAnalysis : public MachineFunctionPass {
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private:
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MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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unsigned NumRegUnits;
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/// Instruction that defined each register, relative to the beginning of the
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/// current basic block. When a LiveRegsDefInfo is used to represent a
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/// live-out register, this value is relative to the end of the basic block,
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/// so it will be a negative number.
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using LiveRegsDefInfo = std::vector<int>;
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LiveRegsDefInfo LiveRegs;
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/// Keeps clearance information for all registers. Note that this
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/// is different from the usual definition notion of liveness. The CPU
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/// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = SmallVector<LiveRegsDefInfo, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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/// Current instruction number.
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/// The first instruction in each basic block is 0.
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int CurInstr;
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/// Maps instructions to their instruction Ids, relative to the begining of
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/// their basic blocks.
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DenseMap<MachineInstr *, int> InstIds;
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/// All reaching defs of a given RegUnit for a given MBB.
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using MBBRegUnitDefs = SmallVector<int, 1>;
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/// All reaching defs of all reg units for a given MBB
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using MBBDefsInfo = std::vector<MBBRegUnitDefs>;
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/// All reaching defs of all reg units for a all MBBs
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using MBBReachingDefsInfo = SmallVector<MBBDefsInfo, 4>;
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MBBReachingDefsInfo MBBReachingDefs;
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/// Default values are 'nothing happened a long time ago'.
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const int ReachingDefDefaultVal = -(1 << 20);
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public:
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static char ID; // Pass identification, replacement for typeid
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ReachingDefAnalysis() : MachineFunctionPass(ID) {
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initializeReachingDefAnalysisPass(*PassRegistry::getPassRegistry());
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}
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void releaseMemory() override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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/// Provides the instruction id of the closest reaching def instruction of
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/// PhysReg that reaches MI, relative to the begining of MI's basic block.
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int getReachingDef(MachineInstr *MI, int PhysReg);
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/// Provides the clearance - the number of instructions since the closest
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/// reaching def instuction of PhysReg that reaches MI.
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int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
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private:
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/// Set up LiveRegs by merging predecessor live-out values.
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void enterBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Update live-out values.
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void leaveBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Process he given basic block.
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void processBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Update def-ages for registers defined by MI.
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/// Also break dependencies on partial defs and undef uses.
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void processDefs(MachineInstr *);
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};
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} // namespace llvm
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#endif // LLVM_CODEGEN_REACHINGDEFSANALYSIS_H
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