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For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change. For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as .quad .L2-.L1, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above. This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for. For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker. Differential Revision: https://reviews.llvm.org/D45181 Patch by Simon Cook. llvm-svn: 333079
131 lines
4.4 KiB
C++
131 lines
4.4 KiB
C++
//===- MCAsmBackend.cpp - Target MC Assembly Backend ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/ADT/None.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCCodePadder.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCWasmObjectWriter.h"
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#include "llvm/MC/MCWinCOFFObjectWriter.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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using namespace llvm;
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MCAsmBackend::MCAsmBackend(support::endianness Endian)
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: CodePadder(new MCCodePadder()), Endian(Endian) {}
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MCAsmBackend::~MCAsmBackend() = default;
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std::unique_ptr<MCObjectWriter>
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MCAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
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auto TW = createObjectTargetWriter();
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switch (TW->getFormat()) {
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case Triple::ELF:
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return createELFObjectWriter(cast<MCELFObjectTargetWriter>(std::move(TW)), OS,
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Endian == support::little);
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case Triple::MachO:
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return createMachObjectWriter(cast<MCMachObjectTargetWriter>(std::move(TW)),
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OS, Endian == support::little);
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case Triple::COFF:
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return createWinCOFFObjectWriter(
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cast<MCWinCOFFObjectTargetWriter>(std::move(TW)), OS);
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case Triple::Wasm:
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return createWasmObjectWriter(cast<MCWasmObjectTargetWriter>(std::move(TW)),
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OS);
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default:
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llvm_unreachable("unexpected object format");
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}
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}
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std::unique_ptr<MCObjectWriter>
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MCAsmBackend::createDwoObjectWriter(raw_pwrite_stream &OS,
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raw_pwrite_stream &DwoOS) const {
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auto TW = createObjectTargetWriter();
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if (TW->getFormat() != Triple::ELF)
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report_fatal_error("dwo only supported with ELF");
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return createELFDwoObjectWriter(cast<MCELFObjectTargetWriter>(std::move(TW)),
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OS, DwoOS, Endian == support::little);
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}
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Optional<MCFixupKind> MCAsmBackend::getFixupKind(StringRef Name) const {
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return None;
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}
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const MCFixupKindInfo &MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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static const MCFixupKindInfo Builtins[] = {
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{"FK_Data_1", 0, 8, 0},
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{"FK_Data_2", 0, 16, 0},
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{"FK_Data_4", 0, 32, 0},
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{"FK_Data_8", 0, 64, 0},
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{"FK_PCRel_1", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
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{"FK_PCRel_2", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
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{"FK_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"FK_PCRel_8", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
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{"FK_GPRel_1", 0, 8, 0},
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{"FK_GPRel_2", 0, 16, 0},
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{"FK_GPRel_4", 0, 32, 0},
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{"FK_GPRel_8", 0, 64, 0},
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{"FK_DTPRel_4", 0, 32, 0},
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{"FK_DTPRel_8", 0, 64, 0},
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{"FK_TPRel_4", 0, 32, 0},
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{"FK_TPRel_8", 0, 64, 0},
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{"FK_SecRel_1", 0, 8, 0},
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{"FK_SecRel_2", 0, 16, 0},
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{"FK_SecRel_4", 0, 32, 0},
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{"FK_SecRel_8", 0, 64, 0},
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{"FK_Data_Add_1", 0, 8, 0},
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{"FK_Data_Add_2", 0, 16, 0},
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{"FK_Data_Add_4", 0, 32, 0},
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{"FK_Data_Add_8", 0, 64, 0},
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{"FK_Data_Sub_1", 0, 8, 0},
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{"FK_Data_Sub_2", 0, 16, 0},
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{"FK_Data_Sub_4", 0, 32, 0},
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{"FK_Data_Sub_8", 0, 64, 0}};
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assert((size_t)Kind <= array_lengthof(Builtins) && "Unknown fixup kind");
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return Builtins[Kind];
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}
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bool MCAsmBackend::fixupNeedsRelaxationAdvanced(
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const MCFixup &Fixup, bool Resolved, uint64_t Value,
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const MCRelaxableFragment *DF, const MCAsmLayout &Layout,
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const bool WasForced) const {
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if (!Resolved)
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return true;
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return fixupNeedsRelaxation(Fixup, Value, DF, Layout);
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}
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void MCAsmBackend::handleCodePaddingBasicBlockStart(
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MCObjectStreamer *OS, const MCCodePaddingContext &Context) {
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CodePadder->handleBasicBlockStart(OS, Context);
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}
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void MCAsmBackend::handleCodePaddingBasicBlockEnd(
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const MCCodePaddingContext &Context) {
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CodePadder->handleBasicBlockEnd(Context);
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}
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void MCAsmBackend::handleCodePaddingInstructionBegin(const MCInst &Inst) {
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CodePadder->handleInstructionBegin(Inst);
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}
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void MCAsmBackend::handleCodePaddingInstructionEnd(const MCInst &Inst) {
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CodePadder->handleInstructionEnd(Inst);
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}
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bool MCAsmBackend::relaxFragment(MCPaddingFragment *PF, MCAsmLayout &Layout) {
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return CodePadder->relaxFragment(PF, Layout);
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}
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