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852739ecc8
Some VLIW instruction sets are Very Long Indeed. Using uint64_t constricts the Inst encoding to 64 bits (naturally).
This change switches CodeEmitter to a mode that uses APInts when Inst's bitwidth is > 64 bits (NFC for existing targets).
When Inst.BitWidth > 64 the prototype changes to:
void TargetMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
SmallVectorImpl<MCFixup> &Fixups,
APInt &Inst,
APInt &Scratch,
const MCSubtargetInfo &STI);
The Inst parameter returns the encoded instruction, the Scratch parameter is used internally for manipulating operands and is exposed so that the underlying storage can be reused between calls to getBinaryCodeForInstr. The goal is to elide any APInt constructions that we can.
Similarly the operand encoding prototype changes to:
getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI);
That is, the operand is passed by reference as APInt rather than returned as uint64_t.
To reiterate, this APInt mode is enabled only when Inst.BitWidth > 64, so this change is NFC for existing targets.
llvm-svn: 371928
37 lines
741 B
TableGen
37 lines
741 B
TableGen
// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
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// Check that EncoderMethod for RegisterOperand is working correctly
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
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def RegOperand : RegisterOperand<RegClass> {
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let EncoderMethod = "barEncoder";
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}
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def foo : Instruction {
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let Size = 1;
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let OutOperandList = (outs);
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let InOperandList = (ins RegOperand:$bar);
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bits<8> bar;
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bits<8> Inst = bar;
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}
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// CHECK: case ::foo: {
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// CHECK: op = barEncoder
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// CHECK: op &= UINT64_C(255);
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// CHECK: Value |= op;
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// CHECK: break;
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// CHECK: }
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