Cullen Rhodes e25a1a8f41 [AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME) ... First patch in a series adding MC layer support for the Arm Scalable Matrix Extension. This patch adds the following features: sme, sme-i64, sme-f64 The sme-i64 and sme-f64 flags are for the optional I16I64 and F64F64 features. If a target supports I16I64 then the following instructions are implemented: * 64-bit integer ADDHA and ADDVA variants (D105570). * SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS instructions that accumulate 16-bit integer outer products into 64-bit integer tiles. If a target supports F64F64 then the FMOPA and FMOPS instructions that accumulate double-precision floating-point outer products into double-precision tiles are implemented. Outer products are implemented in D105571. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06 Reviewed By: CarolineConcatto Differential Revision: https://reviews.llvm.org/D105569		2021-07-12 13:28:10 +00:00
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llvm	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
llvm-c	[Orc] At CBindings for LazyRexports	2021-07-01 21:52:05 +02:00