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https://github.com/RPCS3/llvm-mirror.git
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aadd018f63
This patch adds a new option to enable/disable register renaming in the load-store optimizer. Defaults to disabled, as there is a potential mis-compile caused by this.
275 lines
9.3 KiB
LLVM
275 lines
9.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-ios7.0.0 -mcpu=cyclone -enable-misched=false | FileCheck %s
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; rdar://13625505
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; Here we have 9 fixed integer arguments the 9th argument in on stack, the
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; varargs start right after at 8-byte alignment.
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define void @fn9(i32* %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, ...) nounwind noinline ssp {
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; CHECK-LABEL: fn9:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub sp, sp, #64 ; =64
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; CHECK-NEXT: ldr w8, [sp, #64]
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; CHECK-NEXT: stp w2, w1, [sp, #52]
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; CHECK-NEXT: stp w4, w3, [sp, #44]
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; CHECK-NEXT: stp w6, w5, [sp, #36]
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; CHECK-NEXT: str w7, [sp, #32]
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: ldr w9, [sp, #72]
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; CHECK-NEXT: ldr w8, [sp, #80]
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; CHECK-NEXT: stp w8, w9, [sp, #16]
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; CHECK-NEXT: add x8, sp, #72 ; =72
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; CHECK-NEXT: add x8, x8, #24 ; =24
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; CHECK-NEXT: str x8, [sp, #24]
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; CHECK-NEXT: ldr w8, [sp, #88]
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; CHECK-NEXT: str w8, [sp, #12]
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; CHECK-NEXT: add sp, sp, #64 ; =64
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; CHECK-NEXT: ret
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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%7 = alloca i32, align 4
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%8 = alloca i32, align 4
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%9 = alloca i32, align 4
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%args = alloca i8*, align 8
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%a10 = alloca i32, align 4
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%a11 = alloca i32, align 4
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%a12 = alloca i32, align 4
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store i32 %a2, i32* %2, align 4
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store i32 %a3, i32* %3, align 4
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store i32 %a4, i32* %4, align 4
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store i32 %a5, i32* %5, align 4
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store i32 %a6, i32* %6, align 4
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store i32 %a7, i32* %7, align 4
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store i32 %a8, i32* %8, align 4
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store i32 %a9, i32* %9, align 4
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store i32 %a9, i32* %a1
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%10 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %10)
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%11 = va_arg i8** %args, i32
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store i32 %11, i32* %a10, align 4
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%12 = va_arg i8** %args, i32
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store i32 %12, i32* %a11, align 4
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%13 = va_arg i8** %args, i32
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store i32 %13, i32* %a12, align 4
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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define i32 @main() nounwind ssp {
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; CHECK-LABEL: main:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: sub sp, sp, #96 ; =96
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; CHECK-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
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; CHECK-NEXT: mov w9, #1
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; CHECK-NEXT: mov w8, #2
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; CHECK-NEXT: stp w8, w9, [sp, #72]
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; CHECK-NEXT: mov w9, #3
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; CHECK-NEXT: mov w8, #4
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; CHECK-NEXT: stp w8, w9, [sp, #64]
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; CHECK-NEXT: mov w9, #5
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; CHECK-NEXT: mov w8, #6
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; CHECK-NEXT: stp w8, w9, [sp, #56]
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; CHECK-NEXT: mov w9, #7
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; CHECK-NEXT: mov w8, #8
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; CHECK-NEXT: stp w8, w9, [sp, #48]
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; CHECK-NEXT: mov w8, #9
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; CHECK-NEXT: mov w9, #10
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; CHECK-NEXT: stp w9, w8, [sp, #40]
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; CHECK-NEXT: mov w10, #11
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; CHECK-NEXT: mov w11, #12
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; CHECK-NEXT: stp w11, w10, [sp, #32]
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; CHECK-NEXT: stp x10, x11, [sp, #16]
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; CHECK-NEXT: str x9, [sp, #8]
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; CHECK-NEXT: str w8, [sp]
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; CHECK-NEXT: add x0, sp, #76 ; =76
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; CHECK-NEXT: mov w1, #2
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; CHECK-NEXT: mov w2, #3
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; CHECK-NEXT: mov w3, #4
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; CHECK-NEXT: mov w4, #5
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; CHECK-NEXT: mov w5, #6
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; CHECK-NEXT: mov w6, #7
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; CHECK-NEXT: mov w7, #8
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; CHECK-NEXT: bl _fn9
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; CHECK-NEXT: mov w0, #0
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; CHECK-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #96 ; =96
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; CHECK-NEXT: ret
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%a1 = alloca i32, align 4
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%a2 = alloca i32, align 4
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%a3 = alloca i32, align 4
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%a4 = alloca i32, align 4
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%a5 = alloca i32, align 4
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%a6 = alloca i32, align 4
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%a7 = alloca i32, align 4
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%a8 = alloca i32, align 4
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%a9 = alloca i32, align 4
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%a10 = alloca i32, align 4
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%a11 = alloca i32, align 4
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%a12 = alloca i32, align 4
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store i32 1, i32* %a1, align 4
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store i32 2, i32* %a2, align 4
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store i32 3, i32* %a3, align 4
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store i32 4, i32* %a4, align 4
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store i32 5, i32* %a5, align 4
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store i32 6, i32* %a6, align 4
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store i32 7, i32* %a7, align 4
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store i32 8, i32* %a8, align 4
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store i32 9, i32* %a9, align 4
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store i32 10, i32* %a10, align 4
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store i32 11, i32* %a11, align 4
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store i32 12, i32* %a12, align 4
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%1 = load i32, i32* %a1, align 4
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%2 = load i32, i32* %a2, align 4
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%3 = load i32, i32* %a3, align 4
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%4 = load i32, i32* %a4, align 4
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%5 = load i32, i32* %a5, align 4
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%6 = load i32, i32* %a6, align 4
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%7 = load i32, i32* %a7, align 4
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%8 = load i32, i32* %a8, align 4
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%9 = load i32, i32* %a9, align 4
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%10 = load i32, i32* %a10, align 4
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%11 = load i32, i32* %a11, align 4
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%12 = load i32, i32* %a12, align 4
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call void (i32*, i32, i32, i32, i32, i32, i32, i32, i32, ...) @fn9(i32* %a1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12)
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ret i32 0
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}
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;rdar://13668483
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@.str = private unnamed_addr constant [4 x i8] c"fmt\00", align 1
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define void @foo(i8* %fmt, ...) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #48 ; =48
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; CHECK-NEXT: ldr w8, [sp, #48]
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; CHECK-NEXT: str w8, [sp, #28]
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; CHECK-NEXT: add x8, sp, #48 ; =48
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; CHECK-NEXT: add x8, x8, #23 ; =23
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; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
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; CHECK-NEXT: add x9, x8, #16 ; =16
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; CHECK-NEXT: stp x9, x0, [sp, #32]
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; CHECK-NEXT: ldr q0, [x8]
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; CHECK-NEXT: str q0, [sp], #48
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; CHECK-NEXT: ret
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entry:
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%fmt.addr = alloca i8*, align 8
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%args = alloca i8*, align 8
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%vc = alloca i32, align 4
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%vv = alloca <4 x i32>, align 16
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store i8* %fmt, i8** %fmt.addr, align 8
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%args1 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %args1)
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%0 = va_arg i8** %args, i32
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store i32 %0, i32* %vc, align 4
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%1 = va_arg i8** %args, <4 x i32>
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store <4 x i32> %1, <4 x i32>* %vv, align 16
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ret void
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}
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define void @bar(i32 %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: bar:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #80 ; =80
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; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
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; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: str w0, [sp, #60]
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; CHECK-NEXT: stp q0, q0, [sp, #16]
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; CHECK-NEXT: str x0, [sp]
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; CHECK-NEXT: Lloh0:
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; CHECK-NEXT: adrp x0, l_.str@PAGE
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; CHECK-NEXT: Lloh1:
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; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF
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; CHECK-NEXT: bl _foo
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; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #80 ; =80
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpAdd Lloh0, Lloh1
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entry:
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%x.addr = alloca i32, align 4
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%y.addr = alloca <4 x i32>, align 16
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store i32 %x, i32* %x.addr, align 4
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store <4 x i32> %y, <4 x i32>* %y.addr, align 16
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%0 = load i32, i32* %x.addr, align 4
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%1 = load <4 x i32>, <4 x i32>* %y.addr, align 16
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call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
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ret void
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}
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; rdar://13668927
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; When passing 16-byte aligned small structs as vararg, make sure the caller
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; side is 16-byte aligned on stack.
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%struct.s41 = type { i32, i16, i32, i16 }
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define void @foo2(i8* %fmt, ...) nounwind {
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; CHECK-LABEL: foo2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #48 ; =48
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; CHECK-NEXT: ldr w8, [sp, #48]
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; CHECK-NEXT: str w8, [sp, #28]
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; CHECK-NEXT: add x8, sp, #48 ; =48
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; CHECK-NEXT: add x8, x8, #23 ; =23
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; CHECK-NEXT: and x8, x8, #0xfffffffffffffff0
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; CHECK-NEXT: add x9, x8, #16 ; =16
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; CHECK-NEXT: stp x9, x0, [sp, #32]
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; CHECK-NEXT: ldr q0, [x8]
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; CHECK-NEXT: str q0, [sp], #48
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; CHECK-NEXT: ret
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entry:
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%fmt.addr = alloca i8*, align 8
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%args = alloca i8*, align 8
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%vc = alloca i32, align 4
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%vs = alloca %struct.s41, align 16
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store i8* %fmt, i8** %fmt.addr, align 8
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%args1 = bitcast i8** %args to i8*
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call void @llvm.va_start(i8* %args1)
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%0 = va_arg i8** %args, i32
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store i32 %0, i32* %vc, align 4
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%ap.cur = load i8*, i8** %args
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%1 = getelementptr i8, i8* %ap.cur, i32 15
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%2 = ptrtoint i8* %1 to i64
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%3 = and i64 %2, -16
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%ap.align = inttoptr i64 %3 to i8*
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%ap.next = getelementptr i8, i8* %ap.align, i32 16
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store i8* %ap.next, i8** %args
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%4 = bitcast i8* %ap.align to %struct.s41*
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%5 = bitcast %struct.s41* %vs to i8*
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%6 = bitcast %struct.s41* %4 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 %5, i8* align 16 %6, i64 16, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
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define void @bar2(i32 %x, i128 %s41.coerce) nounwind {
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; CHECK-LABEL: bar2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub sp, sp, #80 ; =80
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; CHECK-NEXT: stp x29, x30, [sp, #64] ; 16-byte Folded Spill
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; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: str w0, [sp, #60]
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; CHECK-NEXT: stp x1, x2, [sp, #32]
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; CHECK-NEXT: stp x1, x2, [sp, #16]
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; CHECK-NEXT: str x0, [sp]
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; CHECK-NEXT: Lloh2:
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; CHECK-NEXT: adrp x0, l_.str@PAGE
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; CHECK-NEXT: Lloh3:
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; CHECK-NEXT: add x0, x0, l_.str@PAGEOFF
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; CHECK-NEXT: bl _foo2
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; CHECK-NEXT: ldp x29, x30, [sp, #64] ; 16-byte Folded Reload
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; CHECK-NEXT: add sp, sp, #80 ; =80
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpAdd Lloh2, Lloh3
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entry:
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%x.addr = alloca i32, align 4
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%s41 = alloca %struct.s41, align 16
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store i32 %x, i32* %x.addr, align 4
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%0 = bitcast %struct.s41* %s41 to i128*
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store i128 %s41.coerce, i128* %0, align 1
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%1 = load i32, i32* %x.addr, align 4
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%2 = bitcast %struct.s41* %s41 to i128*
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%3 = load i128, i128* %2, align 1
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call void (i8*, ...) @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3)
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ret void
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}
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