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llvm-mirror/test/CodeGen/AArch64/arm64_32-null.ll
Tim Northover 1bb14916f2 AArch64: support arm64_32, an ILP32 slice for watchOS.
This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM.
FastISel is mostly disabled for now since it would generate incorrect code for
ILP32.

llvm-svn: 371722
2019-09-12 10:22:23 +00:00

29 lines
679 B
LLVM

; RUN: llc -fast-isel=true -global-isel=false -O0 -mtriple=arm64_32-apple-ios %s -o - | FileCheck %s
; RUN: llc -fast-isel=false -global-isel=false -O0 -mtriple=arm64_32-apple-ios %s -o - | FileCheck %s
define void @test_store(i8** %p) {
; CHECK-LABEL: test_store:
; CHECK: mov [[R1:w[0-9]+]], wzr
; CHECK: str [[R1]], [x0]
store i8* null, i8** %p
ret void
}
define void @test_phi(i8** %p) {
; CHECK-LABEL: test_phi:
; CHECK: mov [[R1:x[0-9]+]], xzr
; CHECK: str [[R1]], [sp]
; CHECK: b [[BB:LBB[0-9_]+]]
; CHECK: [[BB]]:
; CHECK: ldr x0, [sp]
; CHECK: str w0, [x{{.*}}]
bb0:
br label %bb1
bb1:
%tmp0 = phi i8* [ null, %bb0 ]
store i8* %tmp0, i8** %p
ret void
}