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f7143dfdb4
We use extact_subvector and insert_subvector to "cast" between fixed length and scalable vectors. This patch adds custom c++ based ISel for the following cases: fixed_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0 scalable_vector = ISD::INSERT_SUBVECTOR undef(scalable_vector), fixed_vector, 0 Which result in either EXTRACT_SUBREG/INSERT_SUBREG for NEON sized vectors or COPY_TO_REGCLASS otherwise. Differential Revision: https://reviews.llvm.org/D82871
89 lines
4.4 KiB
LLVM
89 lines
4.4 KiB
LLVM
; RUN: llc -aarch64-sve-vector-bits-min=128 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefix=NO_SVE
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; RUN: llc -aarch64-sve-vector-bits-min=256 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK
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; RUN: llc -aarch64-sve-vector-bits-min=384 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK
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; RUN: llc -aarch64-sve-vector-bits-min=512 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=640 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=768 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=896 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=1024 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1152 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1280 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1408 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1536 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1664 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1792 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=1920 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
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; RUN: llc -aarch64-sve-vector-bits-min=2048 -aarch64-enable-atomic-cfg-tidy=false < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
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; Test we can code generater patterns of the form:
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; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0
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; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0
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;
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; NOTE: Currently shufflevector does not support scalable vectors so it cannot
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; be used to model the above operations. Instead these tests rely on knowing
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; how fixed length operation are lowered to scalable ones, with multiple blocks
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; ensuring insert/extract sequences are not folded away.
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target triple = "aarch64-unknown-linux-gnu"
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; Don't use SVE when its registers are no bigger than NEON.
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; NO_SVE-NOT: ptrue
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define void @subvector_v8i32(<8 x i32> *%in, <8 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v8i32:
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; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
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; CHECK: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; CHECK: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECK: ret
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%a = load <8 x i32>, <8 x i32>* %in
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br label %bb1
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bb1:
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store <8 x i32> %a, <8 x i32>* %out
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ret void
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}
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define void @subvector_v16i32(<16 x i32> *%in, <16 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v16i32:
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; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
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; VBITS_GE_512: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; VBITS_GE_512: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECKT: ret
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%a = load <16 x i32>, <16 x i32>* %in
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br label %bb1
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bb1:
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store <16 x i32> %a, <16 x i32>* %out
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ret void
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}
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define void @subvector_v32i32(<32 x i32> *%in, <32 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v32i32:
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; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
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; VBITS_GE_1024: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; VBITS_GE_1024: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECK: ret
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%a = load <32 x i32>, <32 x i32>* %in
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br label %bb1
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bb1:
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store <32 x i32> %a, <32 x i32>* %out
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ret void
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}
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define void @subvector_v64i32(<64 x i32> *%in, <64 x i32>* %out) #0 {
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; CHECK-LABEL: subvector_v64i32:
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; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
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; VBITS_GE_2048: ld1w { [[DATA:z[0-9]+.s]] }, [[PG]]/z, [x0]
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; VBITS_GE_2048: st1w { [[DATA]] }, [[PG]], [x1]
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; CHECK: ret
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%a = load <64 x i32>, <64 x i32>* %in
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br label %bb1
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bb1:
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store <64 x i32> %a, <64 x i32>* %out
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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