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b0f83ed2ae
Summary: The following intrinsics have been extended to support brain float types: svbfloat16_t svclasta[_bf16](svbool_t pg, svbfloat16_t fallback, svbfloat16_t data) bfloat16_t svclasta[_n_bf16](svbool_t pg, bfloat16_t fallback, svbfloat16_t data) bfloat16_t svlasta[_bf16](svbool_t pg, svbfloat16_t op) svbfloat16_t svclastb[_bf16](svbool_t pg, svbfloat16_t fallback, svbfloat16_t data) bfloat16_t svclastb[_n_bf16](svbool_t pg, bfloat16_t fallback, svbfloat16_t data) bfloat16_t svlastb[_bf16](svbool_t pg, svbfloat16_t op) svbfloat16_t svdup[_n]_bf16(bfloat16_t op) svbfloat16_t svdup[_n]_bf16_m(svbfloat16_t inactive, svbool_t pg, bfloat16_t op) svbfloat16_t svdup[_n]_bf16_x(svbool_t pg, bfloat16_t op) svbfloat16_t svdup[_n]_bf16_z(svbool_t pg, bfloat16_t op) svbfloat16_t svdupq[_n]_bf16(bfloat16_t x0, bfloat16_t x1, bfloat16_t x2, bfloat16_t x3, bfloat16_t x4, bfloat16_t x5, bfloat16_t x6, bfloat16_t x7) svbfloat16_t svdupq_lane[_bf16](svbfloat16_t data, uint64_t index) svbfloat16_t svinsr[_n_bf16](svbfloat16_t op1, bfloat16_t op2) Reviewers: sdesmalen, kmclaughlin, c-rhodes, ctetreau, efriedma Subscribers: tschuett, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D82345
128 lines
5.7 KiB
LLVM
128 lines
5.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; WARN-NOT: warning
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;
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; DUP
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;
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define <vscale x 16 x i8> @dup_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, i8 %b) {
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; CHECK-LABEL: dup_i8:
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; CHECK: mov z0.b, p0/m, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> %a,
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<vscale x 16 x i1> %pg,
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i8 %b)
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ret <vscale x 16 x i8> %out
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}
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define <vscale x 8 x i16> @dup_i16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, i16 %b) {
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; CHECK-LABEL: dup_i16:
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; CHECK: mov z0.h, p0/m, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 8 x i1> %pg,
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i16 %b)
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ret <vscale x 8 x i16> %out
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}
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define <vscale x 4 x i32> @dup_i32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, i32 %b) {
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; CHECK-LABEL: dup_i32:
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; CHECK: mov z0.s, p0/m, w0
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i1> %pg,
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i32 %b)
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ret <vscale x 4 x i32> %out
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}
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define <vscale x 2 x i64> @dup_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, i64 %b) {
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; CHECK-LABEL: dup_i64:
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; CHECK: mov z0.d, p0/m, x0
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i1> %pg,
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i64 %b)
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ret <vscale x 2 x i64> %out
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}
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define <vscale x 8 x half> @dup_f16(<vscale x 8 x half> %a, <vscale x 8 x i1> %pg, half %b) {
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; CHECK-LABEL: dup_f16:
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; CHECK: mov z0.h, p0/m, h1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x half> @llvm.aarch64.sve.dup.nxv8f16(<vscale x 8 x half> %a,
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<vscale x 8 x i1> %pg,
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half %b)
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ret <vscale x 8 x half> %out
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}
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define <vscale x 8 x bfloat> @dup_bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x i1> %pg, bfloat %b) #0 {
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; CHECK-LABEL: dup_bf16:
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; CHECK: mov z0.h, p0/m, h1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> %a,
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<vscale x 8 x i1> %pg,
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bfloat %b)
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ret <vscale x 8 x bfloat> %out
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}
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define <vscale x 4 x float> @dup_f32(<vscale x 4 x float> %a, <vscale x 4 x i1> %pg, float %b) {
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; CHECK-LABEL: dup_f32:
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; CHECK: mov z0.s, p0/m, s1
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; CHECK-NEXT: ret
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.dup.nxv4f32(<vscale x 4 x float> %a,
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<vscale x 4 x i1> %pg,
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float %b)
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ret <vscale x 4 x float> %out
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}
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define <vscale x 2 x double> @dup_f64(<vscale x 2 x double> %a, <vscale x 2 x i1> %pg, double %b) {
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; CHECK-LABEL: dup_f64:
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; CHECK: mov z0.d, p0/m, d1
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; CHECK-NEXT: ret
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%out = call <vscale x 2 x double> @llvm.aarch64.sve.dup.nxv2f64(<vscale x 2 x double> %a,
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<vscale x 2 x i1> %pg,
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double %b)
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ret <vscale x 2 x double> %out
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}
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define <vscale x 8 x bfloat> @test_svdup_n_bf16_z(<vscale x 8 x i1> %pg, bfloat %op) #0 {
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; CHECK-LABEL: test_svdup_n_bf16_z:
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; CHECK: mov z1.h, #0
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; CHECK: mov z1.h, p0/m, h0
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; CHECK: mov z0.d, z1.d
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> zeroinitializer, <vscale x 8 x i1> %pg, bfloat %op)
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ret <vscale x 8 x bfloat> %out
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}
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define <vscale x 8 x bfloat> @test_svdup_n_bf16_m(<vscale x 8 x bfloat> %inactive, <vscale x 8 x i1> %pg, bfloat %op) #0 {
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; CHECK-LABEL: test_svdup_n_bf16_m:
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; CHECK: mov z0.h, p0/m, h1
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> %inactive, <vscale x 8 x i1> %pg, bfloat %op)
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ret <vscale x 8 x bfloat> %out
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}
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define <vscale x 8 x bfloat> @test_svdup_n_bf16_x(<vscale x 8 x i1> %pg, bfloat %op) #0 {
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; CHECK-LABEL: test_svdup_n_bf16_x:
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; CHECK: mov z0.h, p0/m, h0
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat> undef, <vscale x 8 x i1> %pg, bfloat %op)
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ret <vscale x 8 x bfloat> %out
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64)
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declare <vscale x 8 x half> @llvm.aarch64.sve.dup.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.dup.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, bfloat)
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declare <vscale x 4 x float> @llvm.aarch64.sve.dup.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float)
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declare <vscale x 2 x double> @llvm.aarch64.sve.dup.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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