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e2b0519ed8
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
llvm-svn: 174054
164 lines
4.3 KiB
LLVM
164 lines
4.3 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -march=aarch64 | FileCheck %s
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define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
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; CHECK: test_madd32:
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%mid = mul i32 %val1, %val2
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%res = add i32 %val0, %mid
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; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
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; CHECK: test_madd64:
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%mid = mul i64 %val1, %val2
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%res = add i64 %val0, %mid
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; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
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; CHECK: test_msub32:
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%mid = mul i32 %val1, %val2
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%res = sub i32 %val0, %mid
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; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
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; CHECK: test_msub64:
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%mid = mul i64 %val1, %val2
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%res = sub i64 %val0, %mid
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; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK: test_smaddl:
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%ext1 = sext i32 %val1 to i64
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%ext2 = sext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = add i64 %acc, %prod
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; CHECK: smaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK: test_smsubl:
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%ext1 = sext i32 %val1 to i64
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%ext2 = sext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 %acc, %prod
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; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK: test_umaddl:
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%ext1 = zext i32 %val1 to i64
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%ext2 = zext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = add i64 %acc, %prod
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; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
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; CHECK: test_umsubl:
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%ext1 = zext i32 %val1 to i64
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%ext2 = zext i32 %val2 to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 %acc, %prod
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; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smulh(i64 %lhs, i64 %rhs) {
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; CHECK: test_smulh:
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%ext1 = sext i64 %lhs to i128
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%ext2 = sext i64 %rhs to i128
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%res = mul i128 %ext1, %ext2
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%high = lshr i128 %res, 64
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%val = trunc i128 %high to i64
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; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %val
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}
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define i64 @test_umulh(i64 %lhs, i64 %rhs) {
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; CHECK: test_umulh:
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%ext1 = zext i64 %lhs to i128
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%ext2 = zext i64 %rhs to i128
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%res = mul i128 %ext1, %ext2
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%high = lshr i128 %res, 64
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%val = trunc i128 %high to i64
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; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %val
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}
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define i32 @test_mul32(i32 %lhs, i32 %rhs) {
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; CHECK: test_mul32:
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%res = mul i32 %lhs, %rhs
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; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_mul64(i64 %lhs, i64 %rhs) {
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; CHECK: test_mul64:
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%res = mul i64 %lhs, %rhs
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; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
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; CHECK: test_mneg32:
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%prod = mul i32 %lhs, %rhs
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%res = sub i32 0, %prod
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; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i32 %res
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}
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define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
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; CHECK: test_mneg64:
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%prod = mul i64 %lhs, %rhs
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%res = sub i64 0, %prod
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; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smull(i32 %lhs, i32 %rhs) {
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; CHECK: test_smull:
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%ext1 = sext i32 %lhs to i64
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%ext2 = sext i32 %rhs to i64
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%res = mul i64 %ext1, %ext2
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; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umull(i32 %lhs, i32 %rhs) {
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; CHECK: test_umull:
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%ext1 = zext i32 %lhs to i64
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%ext2 = zext i32 %rhs to i64
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%res = mul i64 %ext1, %ext2
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; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
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; CHECK: test_smnegl:
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%ext1 = sext i32 %lhs to i64
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%ext2 = sext i32 %rhs to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 0, %prod
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; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
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; CHECK: test_umnegl:
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%ext1 = zext i32 %lhs to i64
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%ext2 = zext i32 %rhs to i64
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%prod = mul i64 %ext1, %ext2
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%res = sub i64 0, %prod
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; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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ret i64 %res
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}
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