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7a5e15697d
The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
74 lines
2.9 KiB
LLVM
74 lines
2.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; XUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; XUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.amdgcn.rcp.f32(float) #0
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declare double @llvm.amdgcn.rcp.f64(double) #0
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declare double @llvm.sqrt.f64(double) #0
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declare float @llvm.sqrt.f32(float) #0
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; FUNC-LABEL: {{^}}rcp_f32:
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; SI: v_rcp_f32_e32
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define void @rcp_f32(float addrspace(1)* %out, float %src) #1 {
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%rcp = call float @llvm.amdgcn.rcp.f32(float %src) #0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_pat_f32:
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; SI-SAFE: v_rcp_f32_e32
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; XSI-SAFE-SPDENORM-NOT: v_rcp_f32_e32
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define void @rcp_pat_f32(float addrspace(1)* %out, float %src) #1 {
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%rcp = fdiv float 1.0, %src
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_rcp_pat_f32:
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; SI-UNSAFE: v_rsq_f32_e32
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; SI-SAFE: v_sqrt_f32_e32
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; SI-SAFE: v_rcp_f32_e32
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define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #1 {
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%sqrt = call float @llvm.sqrt.f32(float %src) #0
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%rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt) #0
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_f64:
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; SI: v_rcp_f64_e32
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define void @rcp_f64(double addrspace(1)* %out, double %src) #1 {
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%rcp = call double @llvm.amdgcn.rcp.f64(double %src) #0
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_pat_f64:
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; SI: v_rcp_f64_e32
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define void @rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
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%rcp = fdiv double 1.0, %src
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_rcp_pat_f64:
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; SI-UNSAFE: v_rsq_f64_e32
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; SI-SAFE-NOT: v_rsq_f64_e32
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; SI-SAFE: v_sqrt_f64
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; SI-SAFE: v_rcp_f64
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define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
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%sqrt = call double @llvm.sqrt.f64(double %src) #0
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%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt) #0
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store double %rcp, double addrspace(1)* %out, align 8
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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