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https://github.com/RPCS3/llvm-mirror.git
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3a75cd4bf9
With this change, ideally IR pass can always generate llvm.stackguard call to get the stack guard; but for now there are still IR form stack guard customizations around (see getIRStackGuard()). Future SSP customization should go through LOAD_STACK_GUARD. There is a behavior change: stack guard values are not CSEed anymore, since we should never reuse the value in case that it has been spilled (and corrupted). See ssp-guard-spill.ll. This also cause the change of stack size and codegen in X86 and AArch64 test cases. Ideally we'd like to know if the guard created in llvm.stackprotector() gets spilled or not. If the value is spilled, discard the value and reload stack guard; otherwise reuse the value. This can be done by teaching register allocator to know how to rematerialize LOAD_STACK_GUARD and force a rematerialization (which seems hard), or check for spilling in expandPostRAPseudo. It only makes sense when the stack guard is a global variable, which requires more instructions to load. Anyway, this seems to go out of the scope of the current patch. llvm-svn: 266806
228 lines
5.8 KiB
LLVM
228 lines
5.8 KiB
LLVM
; RUN: llc < %s -stack-symbol-ordering=0 -mcpu=generic -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -stack-symbol-ordering=0 -mcpu=generic -stackrealign -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s -check-prefix=FORCE-ALIGN
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; rdar://11496434
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; no VLAs or dynamic alignment
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define i32 @t1() nounwind uwtable ssp {
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entry:
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%a = alloca i32, align 4
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call void @t1_helper(i32* %a) nounwind
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 13
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ret i32 %add
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; CHECK: _t1
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; CHECK-NOT: andq $-{{[0-9]+}}, %rsp
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; CHECK: leaq [[OFFSET:[0-9]*]](%rsp), %rdi
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; CHECK: callq _t1_helper
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; CHECK: movl [[OFFSET]](%rsp), %eax
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; CHECK: addl $13, %eax
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}
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declare void @t1_helper(i32*)
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; dynamic realignment
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define i32 @t2() nounwind uwtable ssp {
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entry:
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%a = alloca i32, align 4
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%v = alloca <8 x float>, align 32
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call void @t2_helper(i32* %a, <8 x float>* %v) nounwind
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 13
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ret i32 %add
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; CHECK: _t2
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: andq $-32, %rsp
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; CHECK: subq ${{[0-9]+}}, %rsp
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;
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; CHECK: leaq {{[0-9]*}}(%rsp), %rdi
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; CHECK: leaq {{[0-9]*}}(%rsp), %rsi
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; CHECK: callq _t2_helper
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;
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; CHECK: movq %rbp, %rsp
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; CHECK: popq %rbp
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}
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declare void @t2_helper(i32*, <8 x float>*)
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; VLAs
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define i32 @t3(i64 %sz) nounwind uwtable ssp {
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entry:
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%a = alloca i32, align 4
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%vla = alloca i32, i64 %sz, align 16
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call void @t3_helper(i32* %a, i32* %vla) nounwind
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 13
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ret i32 %add
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; CHECK: _t3
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK-NOT: andq $-{{[0-9]+}}, %rsp
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; CHECK: subq ${{[0-9]+}}, %rsp
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;
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; CHECK: movq %rbp, %rsp
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; CHECK: popq %rbp
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}
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declare void @t3_helper(i32*, i32*)
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; VLAs + Dynamic realignment
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define i32 @t4(i64 %sz) nounwind uwtable ssp {
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entry:
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%a = alloca i32, align 4
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%v = alloca <8 x float>, align 32
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%vla = alloca i32, i64 %sz, align 16
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call void @t4_helper(i32* %a, i32* %vla, <8 x float>* %v) nounwind
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 13
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ret i32 %add
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; CHECK: _t4
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: pushq %rbx
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; CHECK: andq $-32, %rsp
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; CHECK: subq ${{[0-9]+}}, %rsp
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; CHECK: movq %rsp, %rbx
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;
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; CHECK: leaq {{[0-9]*}}(%rbx), %rdi
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; CHECK: leaq {{[0-9]*}}(%rbx), %rdx
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; CHECK: callq _t4_helper
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;
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; CHECK: leaq -{{[0-9]+}}(%rbp), %rsp
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; CHECK: popq %rbx
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; CHECK: popq %rbp
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}
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declare void @t4_helper(i32*, i32*, <8 x float>*)
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; Spilling an AVX register shouldn't cause dynamic realignment
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define i32 @t5(float* nocapture %f) nounwind uwtable ssp {
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entry:
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%a = alloca i32, align 4
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%0 = bitcast float* %f to <8 x float>*
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%1 = load <8 x float>, <8 x float>* %0, align 32
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call void @t5_helper1(i32* %a) nounwind
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call void @t5_helper2(<8 x float> %1) nounwind
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%2 = load i32, i32* %a, align 4
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%add = add nsw i32 %2, 13
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ret i32 %add
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; CHECK: _t5
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; CHECK: subq ${{[0-9]+}}, %rsp
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;
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; CHECK: vmovaps (%rdi), [[AVXREG:%ymm[0-9]+]]
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; CHECK: vmovups [[AVXREG]], (%rsp)
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; CHECK: leaq {{[0-9]+}}(%rsp), %rdi
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; CHECK: callq _t5_helper1
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; CHECK: vmovups (%rsp), %ymm0
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; CHECK: callq _t5_helper2
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; CHECK: movl {{[0-9]+}}(%rsp), %eax
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}
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declare void @t5_helper1(i32*)
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declare void @t5_helper2(<8 x float>)
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; VLAs + Dynamic realignment + Spill
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; FIXME: RA has already reserved RBX, so we can't do dynamic realignment.
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define i32 @t6(i64 %sz, float* nocapture %f) nounwind uwtable ssp {
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entry:
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; CHECK: _t6
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%a = alloca i32, align 4
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%0 = bitcast float* %f to <8 x float>*
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%1 = load <8 x float>, <8 x float>* %0, align 32
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%vla = alloca i32, i64 %sz, align 16
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call void @t6_helper1(i32* %a, i32* %vla) nounwind
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call void @t6_helper2(<8 x float> %1) nounwind
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%2 = load i32, i32* %a, align 4
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%add = add nsw i32 %2, 13
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ret i32 %add
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}
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declare void @t6_helper1(i32*, i32*)
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declare void @t6_helper2(<8 x float>)
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; VLAs + Dynamic realignment + byval
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; The byval adjust the sp after the prolog, but if we're restoring the sp from
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; the base pointer we use the original adjustment.
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%struct.struct_t = type { [5 x i32] }
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define void @t7(i32 %size, %struct.struct_t* byval align 8 %arg1) nounwind uwtable {
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entry:
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%x = alloca i32, align 32
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store i32 0, i32* %x, align 32
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%0 = zext i32 %size to i64
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%vla = alloca i32, i64 %0, align 16
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%1 = load i32, i32* %x, align 32
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call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval align 8 %arg1)
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ret void
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; CHECK: _t7
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; CHECK: pushq %rbp
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; CHECK: movq %rsp, %rbp
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; CHECK: pushq %rbx
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; CHECK: andq $-32, %rsp
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; CHECK: subq ${{[0-9]+}}, %rsp
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; CHECK: movq %rsp, %rbx
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; Stack adjustment for byval
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; CHECK: subq {{.*}}, %rsp
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; CHECK: callq _bar
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; CHECK-NOT: addq {{.*}}, %rsp
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; CHECK: leaq -8(%rbp), %rsp
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; CHECK: popq %rbx
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; CHECK: popq %rbp
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}
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declare i8* @llvm.stacksave() nounwind
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declare void @bar(i32, i32*, %struct.struct_t* byval align 8)
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declare void @llvm.stackrestore(i8*) nounwind
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; Test when forcing stack alignment
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define i32 @t8() nounwind uwtable {
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entry:
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%a = alloca i32, align 4
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call void @t1_helper(i32* %a) nounwind
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 13
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ret i32 %add
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; FORCE-ALIGN: _t8
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; FORCE-ALIGN: movq %rsp, %rbp
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; FORCE-ALIGN: andq $-32, %rsp
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; FORCE-ALIGN-NEXT: subq $32, %rsp
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; FORCE-ALIGN: movq %rbp, %rsp
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; FORCE-ALIGN: popq %rbp
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}
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; VLAs
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define i32 @t9(i64 %sz) nounwind uwtable {
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entry:
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%a = alloca i32, align 4
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%vla = alloca i32, i64 %sz, align 16
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call void @t3_helper(i32* %a, i32* %vla) nounwind
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%0 = load i32, i32* %a, align 4
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%add = add nsw i32 %0, 13
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ret i32 %add
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; FORCE-ALIGN: _t9
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; FORCE-ALIGN: pushq %rbp
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; FORCE-ALIGN: movq %rsp, %rbp
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; FORCE-ALIGN: pushq %rbx
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; FORCE-ALIGN: andq $-32, %rsp
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; FORCE-ALIGN: subq $32, %rsp
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; FORCE-ALIGN: movq %rsp, %rbx
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; FORCE-ALIGN: leaq -8(%rbp), %rsp
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; FORCE-ALIGN: popq %rbx
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; FORCE-ALIGN: popq %rbp
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}
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