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f0ca422f64
autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
41 lines
1.7 KiB
LLVM
41 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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define <4 x i32> @load_zmov_4i32_to_0zzz(<4 x i32> *%ptr) {
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; SSE-LABEL: load_zmov_4i32_to_0zzz:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load_zmov_4i32_to_0zzz:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; AVX-NEXT: retq
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entry:
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%X = load <4 x i32>, <4 x i32>* %ptr
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%Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
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ret <4 x i32>%Y
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}
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define <2 x i64> @load_zmov_2i64_to_0z(<2 x i64> *%ptr) {
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; SSE-LABEL: load_zmov_2i64_to_0z:
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; SSE: # BB#0: # %entry
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; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: load_zmov_2i64_to_0z:
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; AVX: # BB#0: # %entry
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; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: retq
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entry:
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%X = load <2 x i64>, <2 x i64>* %ptr
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%Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
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ret <2 x i64>%Y
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}
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