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24ba078dcd
The in, out, and sbi/cbi family of instructions seem to require a custom decoder. I'm not exactly sure why and would prefer to convince TableGen to provide the correct decoders for these, but I can't seem to convince it to do so. They simply disassemble without any operands. Differential Revision: https://reviews.llvm.org/D74049
37 lines
1.0 KiB
ArmAsm
37 lines
1.0 KiB
ArmAsm
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
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; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
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foo:
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in r2, 4
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in r9, 6
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in r5, 32
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in r0, 0
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in r31, 0
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in r0, 63
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in r31, 63
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in r20, foo+1
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; CHECK: in r2, 4 ; encoding: [0x24,0xb0]
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; CHECK: in r9, 6 ; encoding: [0x96,0xb0]
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; CHECK: in r5, 32 ; encoding: [0x50,0xb4]
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; CHECK: in r0, 0 ; encoding: [0x00,0xb0]
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; CHECK: in r31, 0 ; encoding: [0xf0,0xb1]
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; CHECK: in r0, 63 ; encoding: [0x0f,0xb6]
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; CHECK: in r31, 63 ; encoding: [0xff,0xb7]
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; CHECK: in r20, foo+1 ; encoding: [0x40'A',0xb1'A']
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; CHECK: ; fixup A - offset: 0, value: foo+1, kind: fixup_port6
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; CHECK-INST: in r2, 4
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; CHECK-INST: in r9, 6
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; CHECK-INST: in r5, 32
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; CHECK-INST: in r0, 0
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; CHECK-INST: in r31, 0
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; CHECK-INST: in r0, 63
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; CHECK-INST: in r31, 63
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; CHECK-INST: in r20, 0
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