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Externally-defined functions with weak linkage should not be tail-called on ARM or AArch64, as the AAELF spec requires normal calls to undefined weak functions to be replaced with a NOP or jump to the next instruction. The behaviour of branch instructions in this situation (as used for tail calls) is implementation-defined, so we cannot rely on the linker replacing the tail call with a return. llvm-svn: 215890
106 lines
2.9 KiB
LLVM
106 lines
2.9 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -tailcallopt | FileCheck %s
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declare fastcc void @callee_stack0()
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declare fastcc void @callee_stack8([8 x i32], i64)
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declare fastcc void @callee_stack16([8 x i32], i64, i64)
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declare extern_weak fastcc void @callee_weak()
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define fastcc void @caller_to0_from0() nounwind {
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; CHECK-LABEL: caller_to0_from0:
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; CHECK-NEXT: // BB
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tail call fastcc void @callee_stack0()
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ret void
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; CHECK-NEXT: b callee_stack0
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}
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define fastcc void @caller_to0_from8([8 x i32], i64) {
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; CHECK-LABEL: caller_to0_from8:
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tail call fastcc void @callee_stack0()
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ret void
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; CHECK: add sp, sp, #16
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; CHECK-NEXT: b callee_stack0
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}
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define fastcc void @caller_to8_from0() {
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; CHECK-LABEL: caller_to8_from0:
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; CHECK: sub sp, sp, #32
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; Key point is that the "42" should go #16 below incoming stack
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; pointer (we didn't have arg space to reuse).
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tail call fastcc void @callee_stack8([8 x i32] undef, i64 42)
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ret void
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; CHECK: str {{x[0-9]+}}, [sp, #16]!
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; CHECK-NEXT: b callee_stack8
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}
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define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
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; CHECK-LABEL: caller_to8_from8:
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; CHECK: sub sp, sp, #16
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; Key point is that the "%a" should go where at SP on entry.
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tail call fastcc void @callee_stack8([8 x i32] undef, i64 42)
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ret void
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; CHECK: str {{x[0-9]+}}, [sp, #16]!
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; CHECK-NEXT: b callee_stack8
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}
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define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
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; CHECK-LABEL: caller_to16_from8:
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; CHECK: sub sp, sp, #16
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; Important point is that the call reuses the "dead" argument space
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; above %a on the stack. If it tries to go below incoming-SP then the
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; callee will not deallocate the space, even in fastcc.
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tail call fastcc void @callee_stack16([8 x i32] undef, i64 42, i64 2)
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: b callee_stack16
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ret void
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}
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define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: caller_to8_from24:
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; CHECK: sub sp, sp, #16
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; Key point is that the "%a" should go where at #16 above SP on entry.
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tail call fastcc void @callee_stack8([8 x i32] undef, i64 42)
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ret void
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; CHECK: str {{x[0-9]+}}, [sp, #32]!
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; CHECK-NEXT: b callee_stack8
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}
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define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
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; CHECK-LABEL: caller_to16_from16:
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; CHECK: sub sp, sp, #16
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; Here we want to make sure that both loads happen before the stores:
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; otherwise either %a or %b will be wrongly clobbered.
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tail call fastcc void @callee_stack16([8 x i32] undef, i64 %b, i64 %a)
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ret void
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; CHECK: ldp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: b callee_stack16
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}
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; Weakly-referenced extern functions cannot be tail-called, as AAELF does
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; not define the behaviour of branch instructions to undefined weak symbols.
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define fastcc void @caller_weak() {
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; CHECK-LABEL: caller_weak:
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; CHECK: bl callee_weak
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tail call void @callee_weak()
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ret void
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}
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