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1b5b817c73
One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196906
323 lines
8.4 KiB
LLVM
323 lines
8.4 KiB
LLVM
; Test 32-bit conditional stores that are presented as selects.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo(i32 *)
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; Test the simple case, with the loaded value first.
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define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r2
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %alt, i32 %orig
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store i32 %res, i32 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 64 bits, with the
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; loaded value first.
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define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%ext = sext i32 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r2
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%ext = sext i32 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; Test cases where the value is explicitly zero-extended to 32 bits, with the
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; loaded value first.
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define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%ext = zext i32 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: %r2
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%ext = zext i32 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i32
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store i32 %trunc, i32 *%ptr
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ret void
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}
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; Check the high end of the aligned ST range.
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define void @f7(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: st %r3, 4092(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 1023
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the next word up, which should use STY instead of ST.
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define void @f8(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: sty %r3, 4096(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 1024
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the high end of the aligned STY range.
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define void @f9(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f9:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: sty %r3, 524284(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131071
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f10(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f10:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, 524288
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 131072
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the low end of the STY range.
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define void @f11(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f11:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: sty %r3, -524288(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131072
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f12(i32 *%base, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f12:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, -524292
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; CHECK: st %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%ptr = getelementptr i32 *%base, i64 -131073
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check that STY allows an index.
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define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f13:
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; CHECK-NOT: %r2
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r2
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; CHECK: sty %r4, 4096(%r3,%r2)
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; CHECK: [[LABEL]]:
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i32 *
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; Check that volatile loads are not matched.
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define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f14:
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; CHECK: l {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: st {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load volatile i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; ...likewise stores. In this case we should have a conditional load into %r3.
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define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f15:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: l %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: st %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store volatile i32 %res, i32 *%ptr
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ret void
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}
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; Check that atomic loads are not matched. The transformation is OK for
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; the "unordered" case tested here, but since we don't try to handle atomic
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; operations at all in this context, it seems better to assert that than
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; to restrict the test to a stronger ordering.
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define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
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; FIXME: should use a normal load instead of CS.
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; CHECK-LABEL: f16:
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; CHECK: l {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: st {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load atomic i32 *%ptr unordered, align 4
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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ret void
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}
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; ...likewise stores.
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define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
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; FIXME: should use a normal store instead of CS.
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; CHECK-LABEL: f17:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: l %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: st %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store atomic i32 %res, i32 *%ptr unordered, align 4
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ret void
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}
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; Try a frame index base.
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define void @f18(i32 %alt, i32 %limit) {
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; CHECK-LABEL: f18:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r15
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; CHECK: st {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: [[LABEL]]:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i32
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call void @foo(i32 *%ptr)
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%cond = icmp ult i32 %limit, 420
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%orig = load i32 *%ptr
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%res = select i1 %cond, i32 %orig, i32 %alt
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store i32 %res, i32 *%ptr
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call void @foo(i32 *%ptr)
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ret void
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}
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