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277138a332
This is causing compilation timeouts on code with long sequences of local values and calls (i.e. foo(1); foo(2); foo(3); ...). It turns out that code coverage instrumentation is a great way to create sequences like this, which how our users ran into the issue in practice. Intel has a tool that detects these kinds of non-linear compile time issues, and Andy Kaylor reported it as PR37010. The current sinking code scans the whole basic block once per local value sink, which happens before emitting each call. In theory, local values should only be introduced to be used by instructions between the current flush point and the last flush point, so we should only need to scan those instructions. llvm-svn: 329822
138 lines
3.2 KiB
LLVM
138 lines
3.2 KiB
LLVM
; RUN: llc -fast-isel-sink-local-values -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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define void @t0(i32 %a) nounwind {
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entry:
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; CHECK: t0
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; CHECK: str {{w[0-9]+}}, [sp, #12]
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; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
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; CHECK-NEXT: str [[REGISTER]], [sp, #12]
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; CHECK: ret
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr
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%tmp = load i32, i32* %a.addr
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store i32 %tmp, i32* %a.addr
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ret void
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}
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define void @t1(i64 %a) nounwind {
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; CHECK: t1
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; CHECK: str {{x[0-9]+}}, [sp, #8]
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; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
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; CHECK-NEXT: str [[REGISTER]], [sp, #8]
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; CHECK: ret
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%a.addr = alloca i64, align 4
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store i64 %a, i64* %a.addr
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%tmp = load i64, i64* %a.addr
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store i64 %tmp, i64* %a.addr
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ret void
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}
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define zeroext i1 @i1(i1 %a) nounwind {
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entry:
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; CHECK: @i1
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; CHECK: and w0, w0, #0x1
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; CHECK: strb w0, [sp, #15]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: and w0, w0, #0x1
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; CHECK: and w0, w0, #0x1
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; CHECK: add sp, sp, #16
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; CHECK: ret
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%a.addr = alloca i1, align 1
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store i1 %a, i1* %a.addr, align 1
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%0 = load i1, i1* %a.addr, align 1
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ret i1 %0
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}
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define i32 @t2(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: ldur w0, [x0, #-4]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -1
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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define i32 @t3(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: ldur w0, [x0, #-256]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -64
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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define void @t4(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: stur wzr, [x0, #-4]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -1
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store i32 0, i32* %0, align 4
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ret void
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}
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define void @t5(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: stur wzr, [x0, #-256]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -64
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store i32 0, i32* %0, align 4
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ret void
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}
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define void @t6() nounwind {
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; CHECK: t6
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; CHECK: brk #0x1
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tail call void @llvm.trap()
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ret void
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}
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declare void @llvm.trap() nounwind
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define void @ands(i32* %addr) {
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; CHECK-LABEL: ands:
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; CHECK: tst [[COND:w[0-9]+]], #0x1
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; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x2
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; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x1
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; CHECK-NEXT: csel [[COND]],
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entry:
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%cond91 = select i1 undef, i32 1, i32 2
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store i32 %cond91, i32* %addr, align 4
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ret void
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}
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define i64 @mul_umul(i64 %arg) {
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; CHECK-LABEL: mul_umul:
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; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
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; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
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entry:
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%sub.ptr.div = sdiv exact i64 %arg, 8
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%tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
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%tmp1 = extractvalue { i64, i1 } %tmp, 0
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ret i64 %tmp1
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}
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
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define void @logicalReg() {
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; Make sure we generate a logical reg = reg, reg instruction without any
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; machine verifier errors.
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; CHECK-LABEL: logicalReg:
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; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
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; CHECK: ret
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entry:
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br i1 undef, label %cond.end, label %cond.false
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cond.false:
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%cond = select i1 undef, i1 true, i1 false
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br label %cond.end
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cond.end:
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%cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
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ret void
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}
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