Matt Arsenault ca4a8cfd5d AMDGPU: Fix disassembly of aperture registers ...

llvm-svn: 295555

2017-02-18 18:41:41 +00:00

..

AArch64

Revert r294437 as it broke an asan buildbot.

2017-02-08 21:41:16 +00:00

AMDGPU

AMDGPU: Fix disassembly of aperture registers

2017-02-18 18:41:41 +00:00

ARM

[ARM] Saturation instructions are DSP-only

2016-07-25 22:25:25 +00:00

Hexagon

[Hexagon] Replace instruction definitions with auto-generated ones

2017-02-10 15:33:13 +00:00

Lanai

[lanai] Add Lanai backend.

2016-03-28 13:09:54 +00:00

Mips

[mips] Correct c.cond.fmt instruction definition.

2017-01-16 13:55:58 +00:00

PowerPC

Add some Book-E instructions to the asm parser and printer.

2017-01-29 04:55:57 +00:00

Sparc

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

2016-03-09 18:20:21 +00:00

SystemZ

[SystemZ] Support remaining atomic instructions

2016-12-02 18:24:16 +00:00

X86

[X86] Clzero intrinsic and its addition under znver1

2017-02-09 04:27:34 +00:00

XCore

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00