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edd7201c9d
Summary: Each OperandPredicateMatcher shouldn't need to know how to generate the expression to reference a MachineOperand. The OperandMatcher should provide it. In addition to separating responsibilities, this also lays some groundwork for decoupling source patterns from destination patterns to allow invented operands or operands provided by GlobalISel's equivalent to the ComplexPattern<> class. Depends on D29709 Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D29710 llvm-svn: 295668
59 lines
2.5 KiB
TableGen
59 lines
2.5 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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//===- Define the necessary boilerplate for our test target. --------------===//
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def R0 : Register<"r0">;
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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class I<dag OOps, dag IOps, list<dag> Pat>
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: Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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//===- Test the function definition boilerplate. --------------------------===//
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// CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I) const {
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// CHECK: const MachineRegisterInfo &MRI = I.getParent()->getParent()->getRegInfo();
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//===- Test a simple pattern with regclass operands. ----------------------===//
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// CHECK: if ((I.getOpcode() == TargetOpcode::G_ADD) &&
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// CHECK-NEXT: ((/* Operand 0 */ (MRI.getType(I.getOperand(0).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* Operand 1 */ (MRI.getType(I.getOperand(1).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI))))) &&
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// CHECK-NEXT: ((/* Operand 2 */ (MRI.getType(I.getOperand(2).getReg()) == (LLT::scalar(32))) &&
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// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(I.getOperand(2).getReg(), MRI, TRI)))))) {
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// CHECK-NEXT: // (add:i32 GPR32:i32:$src1, GPR32:i32:$src2) => (ADD:i32 GPR32:i32:$src1, GPR32:i32:$src2)
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// CHECK-NEXT: I.setDesc(TII.get(MyTarget::ADD));
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// CHECK-NEXT: constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
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[(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
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//===- Test a pattern with an MBB operand. --------------------------------===//
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// CHECK: if ((I.getOpcode() == TargetOpcode::G_BR) &&
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// CHECK-NEXT: ((/* Operand 0 */ (I.getOperand(0).isMBB())))) {
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// CHECK-NEXT: // (br (bb:Other):$target) => (BR (bb:Other):$target)
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// CHECK-NEXT: I.setDesc(TII.get(MyTarget::BR));
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// CHECK-NEXT: constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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// CHECK-NEXT: return true;
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// CHECK-NEXT: }
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def BR : I<(outs), (ins unknown:$target),
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[(br bb:$target)]>;
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