Bradley Smith e3dbaf1580 [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD ...

Adjust generateFMAsInMachineCombiner to return false if SVE is present
in order to combine fmul+fadd into fma. Also add new pseudo instructions
so as to select the most appropriate of FMLA/FMAD depending on register
allocation.

Depends on D96599

Differential Revision: https://reviews.llvm.org/D96424

2021-02-18 16:55:16 +00:00

..

llvm

[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

2021-02-18 16:55:16 +00:00

llvm-c

LLVM-C: Allow LLVM{Get/Set}Alignment on an atomicrmw/cmpxchg instruction.

2021-02-12 18:31:18 -05:00