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2f09b60413
This patch aims to exploit the following vector multiply high instructions on Power10. vmulhsw VRT, VRA, VRB vmulhsd VRT, VRA, VRB vmulhuw VRT, VRA, VRB vmulhud VRT, VRA, VRB Differential Revision: https://reviews.llvm.org/D82584
79 lines
2.5 KiB
LLVM
79 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case aims to test the vector multiply instructions on Power10.
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; This includes the low order and high order versions of vector multiply.
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; The low order version operates on doublewords, whereas the high order version
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; operates on signed and unsigned words and doublewords.
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define <2 x i64> @test_vmulld(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmulld:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmulld v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%mul = mul <2 x i64> %b, %a
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ret <2 x i64> %mul
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}
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define <2 x i64> @test_vmulhsd(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmulhsd:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmulhsd v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%0 = sext <2 x i64> %a to <2 x i128>
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%1 = sext <2 x i64> %b to <2 x i128>
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%mul = mul <2 x i128> %1, %0
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%shr = lshr <2 x i128> %mul, <i128 64, i128 64>
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%tr = trunc <2 x i128> %shr to <2 x i64>
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ret <2 x i64> %tr
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}
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define <2 x i64> @test_vmulhud(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmulhud:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmulhud v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%0 = zext <2 x i64> %a to <2 x i128>
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%1 = zext <2 x i64> %b to <2 x i128>
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%mul = mul <2 x i128> %1, %0
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%shr = lshr <2 x i128> %mul, <i128 64, i128 64>
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%tr = trunc <2 x i128> %shr to <2 x i64>
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ret <2 x i64> %tr
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}
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define <4 x i32> @test_vmulhsw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vmulhsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmulhsw v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%0 = sext <4 x i32> %a to <4 x i64>
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%1 = sext <4 x i32> %b to <4 x i64>
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%mul = mul <4 x i64> %1, %0
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%shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
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%tr = trunc <4 x i64> %shr to <4 x i32>
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ret <4 x i32> %tr
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}
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define <4 x i32> @test_vmulhuw(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test_vmulhuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmulhuw v2, v3, v2
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; CHECK-NEXT: blr
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entry:
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%0 = zext <4 x i32> %a to <4 x i64>
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%1 = zext <4 x i32> %b to <4 x i64>
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%mul = mul <4 x i64> %1, %0
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%shr = lshr <4 x i64> %mul, <i64 32, i64 32, i64 32, i64 32>
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%tr = trunc <4 x i64> %shr to <4 x i32>
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ret <4 x i32> %tr
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}
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