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e3e67d4a0a
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
58 lines
2.0 KiB
LLVM
58 lines
2.0 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "4 machine-licm"
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; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn | FileCheck %s
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; rdar://6627786
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; rdar://7792037
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target triple = "x86_64-apple-darwin10.0"
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%struct.Key = type { i64 }
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%struct.__Rec = type opaque
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%struct.__vv = type { }
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define %struct.__vv* @t(%struct.Key* %desc, i64 %p) nounwind ssp {
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entry:
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br label %bb4
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bb4: ; preds = %bb.i, %bb26, %bb4, %entry
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; CHECK: %bb4
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; CHECK: xorl
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; CHECK: callq
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; CHECK: xorl
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; CHECK: xorl
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; CHECK: movq
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%0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0]
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%ins = or i64 %p, 2097152 ; <i64> [#uses=1]
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%1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1]
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%cond = icmp eq i32 %1, 1 ; <i1> [#uses=1]
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br i1 %cond, label %bb26, label %bb4
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bb26: ; preds = %bb4
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%2 = and i64 %ins, 15728640 ; <i64> [#uses=1]
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%cond.i = icmp eq i64 %2, 1048576 ; <i1> [#uses=1]
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br i1 %cond.i, label %bb.i, label %bb4
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bb.i: ; preds = %bb26
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%3 = load i32* null, align 4 ; <i32> [#uses=1]
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%4 = uitofp i32 %3 to float ; <float> [#uses=1]
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%.sum13.i = add i64 0, 4 ; <i64> [#uses=1]
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%5 = getelementptr i8* null, i64 %.sum13.i ; <i8*> [#uses=1]
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%6 = bitcast i8* %5 to i32* ; <i32*> [#uses=1]
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%7 = load i32* %6, align 4 ; <i32> [#uses=1]
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%8 = uitofp i32 %7 to float ; <float> [#uses=1]
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%.sum.i = add i64 0, 8 ; <i64> [#uses=1]
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%9 = getelementptr i8* null, i64 %.sum.i ; <i8*> [#uses=1]
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%10 = bitcast i8* %9 to i32* ; <i32*> [#uses=1]
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%11 = load i32* %10, align 4 ; <i32> [#uses=1]
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%12 = uitofp i32 %11 to float ; <float> [#uses=1]
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%13 = insertelement <4 x float> undef, float %4, i32 0 ; <<4 x float>> [#uses=1]
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%14 = insertelement <4 x float> %13, float %8, i32 1 ; <<4 x float>> [#uses=1]
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%15 = insertelement <4 x float> %14, float %12, i32 2 ; <<4 x float>> [#uses=1]
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store <4 x float> %15, <4 x float>* null, align 16
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br label %bb4
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}
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declare i32 @xxGetOffsetForCode(...)
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declare i32 @xxCalculateMidType(...)
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