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71 lines
2.6 KiB
TableGen
71 lines
2.6 KiB
TableGen
//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//Alpha is little endian
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//===----------------------------------------------------------------------===//
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// Subtarget Features
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//===----------------------------------------------------------------------===//
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def FeatureCIX : SubtargetFeature<"CIX", "HasCT", "true",
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"Enable CIX extentions">;
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def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
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"Enable FIX extentions">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AlphaRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Schedule Description
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//===----------------------------------------------------------------------===//
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include "AlphaSchedule.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AlphaInstrInfo.td"
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def AlphaInstrInfo : InstrInfo {
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// Define how we want to layout our target-specific information field.
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// let TSFlagsFields = [];
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// let TSFlagsShifts = [];
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}
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//===----------------------------------------------------------------------===//
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// Alpha Processor Definitions
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//===----------------------------------------------------------------------===//
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def : Processor<"generic", Alpha21264Itineraries, []>;
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def : Processor<"pca56" , Alpha21264Itineraries, []>;
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def : Processor<"ev56" , Alpha21264Itineraries, []>;
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def : Processor<"ev6" , Alpha21264Itineraries, [FeatureFIX]>;
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def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
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//===----------------------------------------------------------------------===//
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// The Alpha Target
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//===----------------------------------------------------------------------===//
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def Alpha : Target {
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// Pull in Instruction Info:
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let InstructionSet = AlphaInstrInfo;
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}
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