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https://github.com/RPCS3/llvm-mirror.git
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f4b2751ee6
is currently off by default, and can be enabled with -disable-post-RA-scheduler=false. This doesn't have a significant impact on most code yet because it doesn't yet do anything to address anti-dependencies and it doesn't attempt to disambiguate memory references. Also, several popular targets don't have pipeline descriptions yet. The majority of the changes here are splitting the SelectionDAG-specific code out of ScheduleDAG, so that ScheduleDAG can be moved to libLLVMCodeGen.a. The interface between ScheduleDAG-using code and the rest of the scheduling code is somewhat rough and will evolve. llvm-svn: 59676
58 lines
1.2 KiB
CMake
58 lines
1.2 KiB
CMake
add_llvm_library(LLVMCodeGen
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BranchFolding.cpp
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DeadMachineInstructionElim.cpp
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ELFWriter.cpp
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GCMetadata.cpp
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GCMetadataPrinter.cpp
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GCStrategy.cpp
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IfConversion.cpp
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IntrinsicLowering.cpp
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LLVMTargetMachine.cpp
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LatencyPriorityQueue.cpp
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LiveInterval.cpp
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LiveIntervalAnalysis.cpp
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LiveStackAnalysis.cpp
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LiveVariables.cpp
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LoopAligner.cpp
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LowerSubregs.cpp
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MachOWriter.cpp
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MachineBasicBlock.cpp
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MachineDominators.cpp
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MachineFunction.cpp
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MachineInstr.cpp
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MachineLICM.cpp
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MachineLoopInfo.cpp
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MachineModuleInfo.cpp
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MachinePassRegistry.cpp
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MachineRegisterInfo.cpp
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MachineSink.cpp
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OcamlGC.cpp
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PBQP.cpp
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PHIElimination.cpp
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Passes.cpp
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PostRASchedulerList.cpp
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PreAllocSplitting.cpp
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PrologEpilogInserter.cpp
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PseudoSourceValue.cpp
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RegAllocBigBlock.cpp
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RegAllocLinearScan.cpp
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RegAllocLocal.cpp
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RegAllocPBQP.cpp
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RegAllocSimple.cpp
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RegisterCoalescer.cpp
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RegisterScavenging.cpp
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ScheduleDAG.cpp
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ScheduleDAGEmit.cpp
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ScheduleDAGInstrs.cpp
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ScheduleDAGPrinter.cpp
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ShadowStackGC.cpp
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SimpleRegisterCoalescing.cpp
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StackProtector.cpp
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StackSlotColoring.cpp
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StrongPHIElimination.cpp
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TargetInstrInfoImpl.cpp
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TwoAddressInstructionPass.cpp
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UnreachableBlockElim.cpp
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VirtRegMap.cpp
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)
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